RFC: Lower bound SPI transfer Volume Estimation for A1 Chip Chains
I have been asked from different parties what the maximum chain length of the A1 chips is, and while the specs limits the addressable number of chips to 254, I tried to approach the potential limit from the communication side.
To have the chip continuously hashing, for each nonce range the absolute minimum command sequence consists of
To get a command pushed through the chain of M chips, we need to push
With that, the number of word to write per job to chip N in a M-chip chain is
(30 + 2N - 1) + (4 + 2M) + (5 + 2N - 1)
= (29 + 2N) + (4 + 2M) + (4 + 2N)
= 37 + 4N + 2M
For all chips in chain of M chips:
W = sum(N = 1..M) {37 + 4N + 2M}
= M * (37 + 2M) + 4 * (M * (M + 1) / 2)
= 37M + 2M^2 + 2M^2 + 2M
= 4M^2 + 39M
= M * (4M + 39)
For the ease of calculations, we assume W = 4M * (M + 10)
The lower bound of required words W to transmit for continuous hashing a chain of M chips with that is
1: 44
2: 96
4: 224
8: 576
10: 800
16: 1664
20: 2400
32: 5376
40: 8000
64: 18944
80: 28800
128: 70656
A chip running at 800MHz finishes a nonce range in 4/25 seconds or 160ms.
Assuming an SPI duty cycle of D = 20% (polling causes idle times) the minimum SPI host clock to serve a chain of M chips is
W * 16 * 1/D * 1000 / 160 = W * 500Hz
Minimum host SPI clock frequency to operate a chain of M chips:
1: 0.02MHz
4: 0.11MHz
8: 0.29MHz
16: 0.83MHz
32: 2.69MHz
40: 4.00MHz
64: 9.47MHz
At 800MHz core clock, the A1 internal SPI clock is 12.5MHz. Since it is required to keep external SPI clock below internal, we shall assume 64 chips to be the upper bound chain length to try.
Please review and let me know if something is wrong.
I have been asked from different parties what the maximum chain length of the A1 chips is, and while the specs limits the addressable number of chips to 254, I tried to approach the potential limit from the communication side.
To have the chip continuously hashing, for each nonce range the absolute minimum command sequence consists of
- 1x 07 to send the job; command length: 30 words
- 1x 08 to get the result; command length: 4 words
Note: this is the average - some jobs have more than one result, others have zero - 1x 0a to get the queue state; command length: 5 words
Note: this is the absolute minimum, might need to cycle poll
To get a command pushed through the chain of M chips, we need to push
- 2M words for broadcast commands
- 2N-1 words for unicast commands to chip N
With that, the number of word to write per job to chip N in a M-chip chain is
(30 + 2N - 1) + (4 + 2M) + (5 + 2N - 1)
= (29 + 2N) + (4 + 2M) + (4 + 2N)
= 37 + 4N + 2M
For all chips in chain of M chips:
W = sum(N = 1..M) {37 + 4N + 2M}
= M * (37 + 2M) + 4 * (M * (M + 1) / 2)
= 37M + 2M^2 + 2M^2 + 2M
= 4M^2 + 39M
= M * (4M + 39)
For the ease of calculations, we assume W = 4M * (M + 10)
The lower bound of required words W to transmit for continuous hashing a chain of M chips with that is
1: 44
2: 96
4: 224
8: 576
10: 800
16: 1664
20: 2400
32: 5376
40: 8000
64: 18944
80: 28800
128: 70656
A chip running at 800MHz finishes a nonce range in 4/25 seconds or 160ms.
Assuming an SPI duty cycle of D = 20% (polling causes idle times) the minimum SPI host clock to serve a chain of M chips is
W * 16 * 1/D * 1000 / 160 = W * 500Hz
Minimum host SPI clock frequency to operate a chain of M chips:
1: 0.02MHz
4: 0.11MHz
8: 0.29MHz
16: 0.83MHz
32: 2.69MHz
40: 4.00MHz
64: 9.47MHz
At 800MHz core clock, the A1 internal SPI clock is 12.5MHz. Since it is required to keep external SPI clock below internal, we shall assume 64 chips to be the upper bound chain length to try.
Please review and let me know if something is wrong.
Having our guys have a look will respond this weekend. Thanks for the info Zefir.
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[edit] Looks ok from what our EE said. Carry ON!
Will push to fix. 
Back to drawing board again.... 
