Congratulations, Zefir.
What were the hidden features, which you managed to reverse engineer?
Topic: [CLOSED] Bitmine CoinCraft A1 28nm chip distribution / DIY support - page 22. (Read 81287 times)
December 30, 2013, 07:55:00 PM
December 23, 2013, 11:44:12 PM
Thanks Zefir and Merry Xmas to you as well and prosperous new year.
Is 1st week in January still the possible for these chips?
Is 1st week in January still the possible for these chips?
December 23, 2013, 08:02:17 PM
Update: initial A1 cgminer driver released
DIY folks and miners,
as announced before, some days ago I received one of this FPGA boards to develop the initial cgminer driver. This board is configured to emulate two daisy-chained A1 chips with 4 cores each, running at ~10% of the expected nominal clock. This is as close at it gets without having the real chip in hand, i.e. I was able to implement and test all documented features (plus some I reverse engineered).
While the emulated HW is limited in terms of clock and number of cores, all basic features (hashing, queue management, chaining) are working. At this stage I am quite confident that if the ASIC behaves exactly like emulated, it can start hashing immediately after it is put on its PCB.
I am running the FPGA board connected to a RasPi. Running over night cgminer settles the average hashrate to 650MHps, which corresponds to ~26GHps for the A1 (4x the cores @ 10x the clock).
Those interested can find the cgminer branch on github here.
Wish you all peaceful and pleasant holidays and a truly successful start in 2014 - with chips to play in hand soon.
zefir
DIY folks and miners,
as announced before, some days ago I received one of this FPGA boards to develop the initial cgminer driver. This board is configured to emulate two daisy-chained A1 chips with 4 cores each, running at ~10% of the expected nominal clock. This is as close at it gets without having the real chip in hand, i.e. I was able to implement and test all documented features (plus some I reverse engineered).
While the emulated HW is limited in terms of clock and number of cores, all basic features (hashing, queue management, chaining) are working. At this stage I am quite confident that if the ASIC behaves exactly like emulated, it can start hashing immediately after it is put on its PCB.
I am running the FPGA board connected to a RasPi. Running over night cgminer settles the average hashrate to 650MHps, which corresponds to ~26GHps for the A1 (4x the cores @ 10x the clock).
Those interested can find the cgminer branch on github here.
Wish you all peaceful and pleasant holidays and a truly successful start in 2014 - with chips to play in hand soon.
zefir
December 22, 2013, 08:09:15 AM
The core voltage in turbo mode is 0.85V. The current from datasheet is 30A.
So we have 26W in turbo mode.
But in turbo mode the speed is 40 GH/s and power usage is 1W/GH.
It seems that consumption current must be about 50A in turbo mode.
So we have 26W in turbo mode.
But in turbo mode the speed is 40 GH/s and power usage is 1W/GH.
It seems that consumption current must be about 50A in turbo mode.
Puzzles me also...
December 11, 2013, 12:52:56 PM
The core voltage in turbo mode is 0.85V. The current from datasheet is 30A.
So we have 26W in turbo mode.
But in turbo mode the speed is 40 GH/s and power usage is 1W/GH.
It seems that consumption current must be about 50A in turbo mode.
So we have 26W in turbo mode.
But in turbo mode the speed is 40 GH/s and power usage is 1W/GH.
It seems that consumption current must be about 50A in turbo mode.
December 11, 2013, 12:24:25 PM
Three weeks delay: http://bitmine.ch/?p=4192
3 weeks. Ouch.
December 10, 2013, 12:28:38 PM
Three weeks delay: http://bitmine.ch/?p=4192
December 09, 2013, 06:31:30 AM
Shouldn't Bitmine have received the chips a week or two ago? The apparent silence about that concerns me. Or did I miss something?
"delivery of the first lot of ASICs in the last week of November 2013"
http://bitmine.ch/?p=2049
"delivery of the first lot of ASICs in the last week of November 2013"
http://bitmine.ch/?p=2049
December 08, 2013, 06:43:01 PM
Please keep me updated of chip distribution. I am planning to purchase some chips and design my boards. Thanks
Ditto 
December 08, 2013, 06:36:37 PM
Please keep me updated of chip distribution. I am planning to purchase some chips and design my boards. Thanks
December 08, 2013, 05:17:59 PM
Any news on design contest or chips delivery? It is last day of W49...
Do they plan to open there board design to make it easier?
Do they plan to open there board design to make it easier?
I am also impatiently waiting for news while the expected delivery date for the A1 is approaching fast. All I know is that Bitmine is visiting China these days, so we should have updates early next week.
December 08, 2013, 03:22:01 PM
Any news on design contest or chips delivery? It is last day of W49...
Do they plan to open there board design to make it easier?
Do they plan to open there board design to make it easier?
December 01, 2013, 01:00:34 AM
The design contest is actually excellent news for all the DIYers here. It kinda levels the playing field a bit. Looking forward to seeing how we can get our hands on these chips.
November 30, 2013, 05:23:22 PM
DIY has such an upward battle now..turnaround times too long to keep up
if Avalon didn't shaft the community last summer it would of been a golden time and put a lot of leverage into that segment (ie funds)
good luck all..
if Avalon didn't shaft the community last summer it would of been a golden time and put a lot of leverage into that segment (ie funds)
good luck all..
November 30, 2013, 05:02:56 PM
I am unfortunately only SW-engineer and from my limited understanding of the HW side I got that (among others) the WASP team was in direct contact with Bitmine and clarified remaining issues. With that, IIRC a revised spec was released that the teams found sufficient enough to design with. If that is not the case, please let me know or post open topics here.
As for the reference design, I remember there is a design contest planned, but it seems Bitmine is too busy with development to announce it in time. I will check status and report back.
You wrote what we will get... Now it is a bit unclear so you could say this is this and not what you thought you will get but...As for the reference design, I remember there is a design contest planned, but it seems Bitmine is too busy with development to announce it in time. I will check status and report back.
Chip specifications, design documents, reference software, and everything that is required to design mining rig development will be provided through github incrementally, with a guaranteed availability of all required support material by end of October.
We have chip specifications... Now unless design documents is not some reference board design but document of the chips there is noting there... And since we are talking about reference software I guess it is for design documents board. Right? So that is missing too. So is this document all we will get? I though Bitmine will follow Avalon and BFL way of doing things. We could probably do with just this document but not in a time frame for first chips...EDIT: and probably took board or two to get it right...
The document is all what Bitmine has available for their own design - if you miss something, please name it. You can not compare this to Avalon or BFL - they had already a working design that only needed to be published. Here everybody starts with a chip still in pipeline and there is no single design proven to work around to be named as reference - if you want to compare it, you need to do so with BitFury chips.
Again, I do not know how much is required to enable HW designer to work on a PCB for this chip, but since the WASP team is almost done, I have to assume it is sufficient. Please let me know otherwise which exact information you miss.
November 30, 2013, 04:34:02 PM
I am unfortunately only SW-engineer and from my limited understanding of the HW side I got that (among others) the WASP team was in direct contact with Bitmine and clarified remaining issues. With that, IIRC a revised spec was released that the teams found sufficient enough to design with. If that is not the case, please let me know or post open topics here.
As for the reference design, I remember there is a design contest planned, but it seems Bitmine is too busy with development to announce it in time. I will check status and report back.
You wrote what we will get... Now it is a bit unclear so you could say this is this and not what you thought you will get but...As for the reference design, I remember there is a design contest planned, but it seems Bitmine is too busy with development to announce it in time. I will check status and report back.
Chip specifications, design documents, reference software, and everything that is required to design mining rig development will be provided through github incrementally, with a guaranteed availability of all required support material by end of October.
We have chip specifications... Now unless design documents is not some reference board design but document of the chips there is noting there... And since we are talking about reference software I guess it is for design documents board. Right? So that is missing too. So is this document all we will get? I though Bitmine will follow Avalon and BFL way of doing things. We could probably do with just this document but not in a time frame for first chips...EDIT: and probably took board or two to get it right...
The document is all what Bitmine has available for their own design - if you miss something, please name it. You can not compare this to Avalon or BFL - they had already a working design that only needed to be published. Here everybody starts with a chip still in pipeline and there is no single design proven to work around to be named as reference - if you want to compare it, you need to do so with BitFury chips.
Again, I do not know how much is required to enable HW designer to work on a PCB for this chip, but since the WASP team is almost done, I have to assume it is sufficient. Please let me know otherwise which exact information you miss.
November 30, 2013, 02:16:58 PM
I am unfortunately only SW-engineer and from my limited understanding of the HW side I got that (among others) the WASP team was in direct contact with Bitmine and clarified remaining issues. With that, IIRC a revised spec was released that the teams found sufficient enough to design with. If that is not the case, please let me know or post open topics here.
As for the reference design, I remember there is a design contest planned, but it seems Bitmine is too busy with development to announce it in time. I will check status and report back.
You wrote what we will get... Now it is a bit unclear so you could say this is this and not what you thought you will get but...As for the reference design, I remember there is a design contest planned, but it seems Bitmine is too busy with development to announce it in time. I will check status and report back.
Chip specifications, design documents, reference software, and everything that is required to design mining rig development will be provided through github incrementally, with a guaranteed availability of all required support material by end of October.
We have chip specifications... Now unless design documents is not some reference board design but document of the chips there is noting there... And since we are talking about reference software I guess it is for design documents board. Right? So that is missing too. So is this document all we will get? I though Bitmine will follow Avalon and BFL way of doing things. We could probably do with just this document but not in a time frame for first chips...EDIT: and probably took board or two to get it right...
November 30, 2013, 05:36:53 AM
Did anyone else get this? Or is it added to the documents on github? If not someone should ask Giorgio to do that as soon as possible.
That's included in the git HEAD (p.16), thanks.
This is what I got from Bitmine concerning the contest in a conversation last week.
Quote
[27.11.2013 11:02:49] Giorgio Massarotto: yes
[27.11.2013 11:03:05] Giorgio Massarotto: let me tell you that sample chips are free for anybody making designs based on our chip
[27.11.2013 11:03:09] Giorgio Massarotto: I mean
[27.11.2013 11:03:17] Giorgio Massarotto: you don't have to place a preorder to receive them
[27.11.2013 11:03:26] Giorgio Massarotto: we'll have an open source development contest
[27.11.2013 11:03:33] Giorgio Massarotto: you'll register there and get some sample chips
[27.11.2013 11:03:37] Giorgio Massarotto: just afew
[27.11.2013 11:03:51] darkfriend77: Ok. When will this be opened?
[27.11.2013 11:04:13 | Bearbeitet 11:04:45] darkfriend77: A few will be enough to test out the prototype.
[27.11.2013 11:12:35] Giorgio Massarotto: it will be opened somewhere in the beginning of december
[27.11.2013 11:12:39] Giorgio Massarotto: we were planning to open it much earlier
[27.11.2013 11:12:40] Giorgio Massarotto: but
[27.11.2013 11:12:46] Giorgio Massarotto: we got insultedbecause no samples were available
[27.11.2013 11:12:55] Giorgio Massarotto: so we have moved it till we'll be able to give out free samples
[27.11.2013 11:03:05] Giorgio Massarotto: let me tell you that sample chips are free for anybody making designs based on our chip
[27.11.2013 11:03:09] Giorgio Massarotto: I mean
[27.11.2013 11:03:17] Giorgio Massarotto: you don't have to place a preorder to receive them
[27.11.2013 11:03:26] Giorgio Massarotto: we'll have an open source development contest
[27.11.2013 11:03:33] Giorgio Massarotto: you'll register there and get some sample chips
[27.11.2013 11:03:37] Giorgio Massarotto: just afew
[27.11.2013 11:03:51] darkfriend77: Ok. When will this be opened?
[27.11.2013 11:04:13 | Bearbeitet 11:04:45] darkfriend77: A few will be enough to test out the prototype.
[27.11.2013 11:12:35] Giorgio Massarotto: it will be opened somewhere in the beginning of december
[27.11.2013 11:12:39] Giorgio Massarotto: we were planning to open it much earlier
[27.11.2013 11:12:40] Giorgio Massarotto: but
[27.11.2013 11:12:46] Giorgio Massarotto: we got insultedbecause no samples were available
[27.11.2013 11:12:55] Giorgio Massarotto: so we have moved it till we'll be able to give out free samples
Thanks for sharing.
November 30, 2013, 05:14:01 AM
As for the reference design, I remember there is a design contest planned, but it seems Bitmine is too busy with development to announce it in time. I will check status and report back.
This is what I got from Bitmine concerning the contest in a conversation last week.
Quote
[27.11.2013 11:02:49] Giorgio Massarotto: yes
[27.11.2013 11:03:05] Giorgio Massarotto: let me tell you that sample chips are free for anybody making designs based on our chip
[27.11.2013 11:03:09] Giorgio Massarotto: I mean
[27.11.2013 11:03:17] Giorgio Massarotto: you don't have to place a preorder to receive them
[27.11.2013 11:03:26] Giorgio Massarotto: we'll have an open source development contest
[27.11.2013 11:03:33] Giorgio Massarotto: you'll register there and get some sample chips
[27.11.2013 11:03:37] Giorgio Massarotto: just afew
[27.11.2013 11:03:51] darkfriend77: Ok. When will this be opened?
[27.11.2013 11:04:13 | Bearbeitet 11:04:45] darkfriend77: A few will be enough to test out the prototype.
[27.11.2013 11:12:35] Giorgio Massarotto: it will be opened somewhere in the beginning of december
[27.11.2013 11:12:39] Giorgio Massarotto: we were planning to open it much earlier
[27.11.2013 11:12:40] Giorgio Massarotto: but
[27.11.2013 11:12:46] Giorgio Massarotto: we got insultedbecause no samples were available
[27.11.2013 11:12:55] Giorgio Massarotto: so we have moved it till we'll be able to give out free samples
[27.11.2013 11:03:05] Giorgio Massarotto: let me tell you that sample chips are free for anybody making designs based on our chip
[27.11.2013 11:03:09] Giorgio Massarotto: I mean
[27.11.2013 11:03:17] Giorgio Massarotto: you don't have to place a preorder to receive them
[27.11.2013 11:03:26] Giorgio Massarotto: we'll have an open source development contest
[27.11.2013 11:03:33] Giorgio Massarotto: you'll register there and get some sample chips
[27.11.2013 11:03:37] Giorgio Massarotto: just afew
[27.11.2013 11:03:51] darkfriend77: Ok. When will this be opened?
[27.11.2013 11:04:13 | Bearbeitet 11:04:45] darkfriend77: A few will be enough to test out the prototype.
[27.11.2013 11:12:35] Giorgio Massarotto: it will be opened somewhere in the beginning of december
[27.11.2013 11:12:39] Giorgio Massarotto: we were planning to open it much earlier
[27.11.2013 11:12:40] Giorgio Massarotto: but
[27.11.2013 11:12:46] Giorgio Massarotto: we got insultedbecause no samples were available
[27.11.2013 11:12:55] Giorgio Massarotto: so we have moved it till we'll be able to give out free samples
November 30, 2013, 05:09:48 AM
We got a chip reference spec that was updated not sure if it is in github. I will post the link here we are all about the sharing and I'm sorry if this was not released to everyone. I assumed it was.
https://drive.google.com/file/d/0B3u-c97pGdlfcGlkSHBQLWVRUlE/edit?usp=sharing
This was related to what our Hardware Lead EE asked for in terms of specs to be shown and BitMine did alter the design to take into consideration what he voiced about the spacing and size of the pads on the chip. This should make things when designing the PCB slightly easier and improve the fabrication and the reliability of the pcb / chip contact. If you want more info on that aspect feel free to join the discussion on our project with the EE on Saturday, 1800 Seattle time. PM me your email and I can add you as lurker to our project page and you can join the meeting Saturday if you want.
Did anyone else get this? Or is it added to the documents on github? If not someone should ask Giorgio to do that as soon as possible.
--------
[Edit] I do not see this revision on the github doc. Need to make sure that they add this information to the page. Zefir found it thanks Zefir.
https://drive.google.com/file/d/0B3u-c97pGdlfcGlkSHBQLWVRUlE/edit?usp=sharing
This was related to what our Hardware Lead EE asked for in terms of specs to be shown and BitMine did alter the design to take into consideration what he voiced about the spacing and size of the pads on the chip. This should make things when designing the PCB slightly easier and improve the fabrication and the reliability of the pcb / chip contact. If you want more info on that aspect feel free to join the discussion on our project with the EE on Saturday, 1800 Seattle time. PM me your email and I can add you as lurker to our project page and you can join the meeting Saturday if you want.
Did anyone else get this? Or is it added to the documents on github? If not someone should ask Giorgio to do that as soon as possible.
--------
[Edit]
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