Topic: [CLOSED] Bitmine CoinCraft A1 28nm chip distribution / DIY support - page 23. (Read 81287 times)

Should be the latest revision in https://github.com/bitmine-ch/bitmine - or am I missing something?

Revised docs ?
link ?

I am unfortunately only SW-engineer and from my limited understanding of the HW side I got that (among others) the WASP team was in direct contact with Bitmine and clarified remaining issues. With that, IIRC a revised spec was released that the teams found sufficient enough to design with. If that is not the case, please let me know or post open topics here.

As for the reference design, I remember there is a design contest planned, but it seems Bitmine is too busy with development to announce it in time. I will check status and report back.

What I for sure am committing to (and agreed with Bitmine already) is to cover the SW side of this project. Bitmine will be visiting Innosilicon next week and plans are to grant me access to the FPGA-based chip emulator, so I can work on test and mining SW. With that, there will be a cgminer driver available before first boards are assembled.


I started this thread for the DIY chip distribution only, but somehow it was nominated as the official technical support thread for OpenSource designs. While I am fine with acting as proxy between you and the overloaded Bitmine crew, I myself have been busy over the past 4 weeks and therefore limited to care way less than I would have liked. It is not too late yet, therefore please feel free to demand for what is missing and make this a successful community project.

OK so if everything is still on track where is documentation reference design and programming? There should be published for 29 days at lest... Even if chip is on time that will not help us without having boards ready...

EDIT: I would definitely be interested but with BFL experience that I had(change from sample to production chips)... I really don't know with current data what can be done till I see more data...

Zefir, i am sortig things out for DIY and the only thing wich Stops me is a working PCB. But Yves i am definitely interested.
Till Jan, Feb, mar there will be possibilities

Well we discuss it Saturday at the meeting thanks for the heads up.

That is what I understood from your partner. Alas, first order for Dec/Jan is closed, i.e. I am limited to those 5k chips I offered and plan to supply all ~15 parties that registered so far - therefore 300 per team is the number to look at. Anyway, if you need 500 or more, you are better off buying in volumes from Bitmine directly.

As for the second run: wafers need to be ordered 3 months in advance. Obviously I have to chose between a) first see how they perform to order more for April / May, or b) hope that everything will work as expect and order now for Feb / March. I will do b) for those chips I plan to deploy myself, but can only consider volumes for DIY if I get reliable commitments.

Our group may be interested in supporting some of that 1st quarter purchases Zefir. Depending of course how the prototype meshes with the A1.

Maybe 500 - 1000 off the top of my head if we are happy with the A1 Chip and likely only for January not February or March as we are keen on the Minion following on in February / March.

Update: no news


Hello folks,

been away for a week and flooded with PMs about the status of A1 chips. I really have no news to share, but want at least to forward Bitmine's information that everything is still on track. So please be patient some more days. We are almost in December, so news are due soon.

I know that some of you already started their design and are eager to test it. All I can tell is that you are in the same position as Bitmine - lots of all-but-chips ready stuff waiting to mine. Generally, I can only promise what I get promised from Bitmine (and what they get promised from Innosilicon and what Innosilicon get promised from GF) - and therefore prefer to stick to the facts only.

Needless to say (but since people are asking, given the exchange rate change and the related self-mine aspect), I assure that I will keep what I offered and provide up to 5k chips from the first run to the DIY scene. Mid-term, what I need from you is some realistic feedback on demand for the following wafer runs (February / March 2014). I'd like to prevent the situation we currently have with lots of demand but all chips out of stock - at the same time I can't carry all the risk of buying chips for stock alone. Therefore, if you are working on own designs and have some feeling what your demand will be in March, please let me know. I understand that forecasting 3 months in bitcoin land is pure gamble, but I do not want to gamble alone


That's for now, I'll keep you updated.


Cheers,
zefir

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Solely in order to not lose valuable time, I would like to get at least one copy of the chip to be sure it is operating correctly on the board or be able to fix a potential problem before sending PCBs to production.
Thanks.

I'll jump on this as well, when the new deal is worked out.  Keep us posted.  :-)

edit:  Specifically, very interested in the new process for getting sample chips to do design verification before ordering a large quantity of pcbs.

any chance to participate in the group buy if it goes further?

Well yes and no. Yes since it is not cancellation but no since we will have to make boards in days...

We are ready to pull the trigger... just tell us when!

Sure it is. Updates will be announced when they are available, but so far there are none and we are still assuming that chips will be ready somewhere in December.

No news are good news in this case.

So is this happening or not?

Most appreciated Giorgio.

We are waiting for the details and we are always glad to help resolve issues with limitations in the chip design.

Hi,

Thanks for pointing these things out to us. Please rest assured that nothing has been made on purpose, it is in our obvious interest to help users and OEMs to build devices based on our ASIC, if it wasn't we wouldn't have released the specifications at all.

We forwarded your inquiries to our IC packaging house who's now updating the drawing with the missing quotes. The pins have been spaced a bit more in order to have more than 0.2 mm spacing between the pads on the footprint, as this could cause manufacturing issues when using 70um copper boards (which is a good thing given the very high currents involved). We also asked for footprint and solder paste recommendations.  

A new specification will be published as soon as we have it,

Thanks

Mini-rant from our EE about the latest chip spec update:

1. Why are the designs less specific now Bitmine for the A1 chip?

2. Why haven't you specified the top-to-bottom pad distance, or completely specified the position of the 0.2mm wide pads that carry the signals. Why have you done this? Was it on purpose? Worrying very worrying.

Please note your package has pads only 0.2mm wide and by not specifying your position this leaves us open to losing half of EVERY pad, if we are off in our guesses by only 1/10th of a millimeter. Only 100 microns, right? Please note that adds to the chips professed tolerance in your positioning of 50 microns. This is shocking. You need to include ALL the dimensions in the picture and table as soon as possible.
 
3. In response to a request to move the signals to allow for a ground escape between pins 8 & 9, you have doubled down by newly assigning pin 8 to Vdd (pin 9, a long vertical pad that forms the other side of the requested escape, is also Vdd). And, unfortunately, the pinout drawing is only related to the package drawing, in shapes. We should be happy that, at least, you fixed their pin naming to match the descriptive table that accompanies the drawing but we need Bitmine to really put out documents that are helpful
 
4. We will not be hand assembling A1 chips to the boards. These chips require robotics to have any chance at all and forget about hot-air-rework - if one of these chips is failing, we will have to scrap the whole board, at worst, or ship it with blue-wires and degraded capability at best.

5. Your promise of replacement chips for failed ones won't begin to cover the costs of discarding the whole board. We are going to design in a physical bypass for every chip, even though that will reduce our density by 20% or more in order to protect those doing DYI and others who buy from us.  
 
6. At this point given what we are learning from Bitmine we expect to have two-three re-spins of boards with these chips, before we get the footprint, solder stencil, and reflow curves right. That's four iterations before production... please Bitmine help us reduce that if at all possible by providing some decent chip specs. We want to have a reasonably good chance to succeed with your chips.

Thanks,

The Wasp Team

Just to let you all know, the updated and final specifications of the CoinCraft A1 have been committed to github.

Soon we'll also commit a reference design and cgminer's driver source code.

For anybody that had questions, we tried to address them with our updated datasheet. Shouldn't this be the case, please don't hesitate to ask and I'll try to address the question here.

Thanks!