Thanks Zefir as always a class act.
That is the best move I think.
We will be watching.
Topic: [CLOSED] Bitmine CoinCraft A1 28nm chip distribution / DIY support - page 24. (Read 81287 times)
November 07, 2013, 04:30:41 AM
November 07, 2013, 03:17:53 AM
OK we are week late on documentation(Company time GMT+1)... Do miner protection apply to documentation to?
Also given the rise in BTC / USD are we going to get some relief in terms of costs of the chips Zefir? Or do we have to get Bitmine to do that?
Quote
Pricing
The price per chip is 8% above Bitmine's for lowest order quantity, which for December delivery is set to $5/GHps and corresponds to $108/chip. I am operating only in the BTC domain and set the price using BitPay's exchange rates. With today's rate, the price is 42.5BTC per 50-chip lot (1 THps).
The price per chip is 8% above Bitmine's for lowest order quantity, which for December delivery is set to $5/GHps and corresponds to $108/chip. I am operating only in the BTC domain and set the price using BitPay's exchange rates. With today's rate, the price is 42.5BTC per 50-chip lot (1 THps).
Hello devs and miners,
yes, I am aware that the provided documentation lacks some portion of information and is therefore insufficient to base own designs on. Giorgio has been in Asia over the past few days and I am waiting for him to return with clarifications and finalized specs. Nevertheless, it is a fact that the given deadline for provision of complete design documentation was not reached.
Another issue is this deal's denomination in BTC. As written in the OP, since this is about BTC generating devices, to me pricing them in BTC is only logical. Consequently, I paid my chips with BTC and though it would be a relieving offer to developers to hedge against exchange rate fluctuations. Obviously people would have appreciated that if BTC exchange rate remained around $100 or crashed hard, but with an increase of 150+% this deal naturally looks very unfavorable.
With that lesson learned (pre-ordering / reservation does not work in BTC world), I am going to halt this offer and set it up again
- when I have the chips in hand for immediate delivery
- at current prices without pre-orders / reservation
I am going to refund all down-payments collected so far and hope to have a way better deal to offer with chips in hand.
Stay tuned.
November 07, 2013, 01:37:34 AM
OK we are week late on documentation(Company time GMT+1)... Do miner protection apply to documentation to?
Also given the rise in BTC / USD are we going to get some relief in terms of costs of the chips Zefir? Or do we have to get Bitmine to do that?
Quote
Pricing
The price per chip is 8% above Bitmine's for lowest order quantity, which for December delivery is set to $5/GHps and corresponds to $108/chip. I am operating only in the BTC domain and set the price using BitPay's exchange rates. With today's rate, the price is 42.5BTC per 50-chip lot (1 THps).
The price per chip is 8% above Bitmine's for lowest order quantity, which for December delivery is set to $5/GHps and corresponds to $108/chip. I am operating only in the BTC domain and set the price using BitPay's exchange rates. With today's rate, the price is 42.5BTC per 50-chip lot (1 THps).
November 06, 2013, 06:02:54 PM
OK we are week late on documentation(Company time GMT+1)... Do miner protection apply to documentation to?
November 05, 2013, 06:36:42 AM
Good luck breaking even with these chips, guys: the numbers aren't with you.
Not always about the break even...
It is about rethinking miners as modular for our group because we are looking way beyond the difficulty that is currently going vertical. Can't speak for others developing "one chip" miners.
November 05, 2013, 03:30:14 AM
Good luck breaking even with these chips, guys: the numbers aren't with you.
November 04, 2013, 11:48:41 PM
Confident that Bitmine will provide the details we all need... question is how soon?
Black Arrow should also be releasing their specs for the Minion soon so here is hoping both the A1 and the Minion are well documented this month.
Black Arrow should also be releasing their specs for the Minion soon so here is hoping both the A1 and the Minion are well documented this month.
November 03, 2013, 07:20:55 PM
And lack of documentation is making it impossible to make anything ready for the time chips came out.
November 03, 2013, 05:51:07 PM
Avalon start selling Gen2. 30BTC for 500 chip 1.6Gh
Bitfury still selling and cut prices.
KNC run next bath and only days for HashFast go with production.
For the price and performance of the chip present, we can be forgive himself as a viable alternative.
Bitfury still selling and cut prices.
KNC run next bath and only days for HashFast go with production.
For the price and performance of the chip present, we can be forgive himself as a viable alternative.
November 03, 2013, 07:22:14 AM
Tick tick tock....
the clock... she is a ticking.
the clock... she is a ticking.
November 02, 2013, 06:14:21 PM
I agree with Lucko. I'm interested in doing a design based on these chips, but I'm not going to bother until I know a little more. Where's the rest of the documentation?
November 02, 2013, 01:23:36 PM
Come on chips are coming(I hope) and a lot of documentation is missing. All should be posted by now...
November 01, 2013, 06:57:17 AM
Le bumpty bump... hoping Dick gets a reply soon.
October 29, 2013, 08:20:59 PM
Folks, in your paragraph 1.1, General protocol specifications, you write:
"The CoinCraft A1 uses two SPI ports, one used in slave mode as an input from the uC or
the previous A1 in the chain (pins IN_MOSI, IN_MISO, IN_SCLK, IN_CS) and one in
master mode to the next A1 in the chain (pins OUT_MOSI, OUT_MISO, OUT_SCLK,
OUT_CS), if any."
In your pin descriptions, you use completely different signal names.
http://i.imgur.com/IXQavZw.png
http://i.imgur.com/tRFsGLK.png
It seems reasonable to assume that the above mentioned slave port, meant to be connected to the MCU or a preceding A1 consists of:
and the above mentioned Master port, meant to drive subsequent A1s consists of:
and that SPI signal flow outbound from the MCU will travel from right to left when looking down on a board with "pin" 1 in the upper left corner.
Could you please verify that I have the layout correctly described, please?
In addition, could you please verify the polarity of the chip select signals? Chip select is only rarely active high, and my controller is wired for the usual active low chip selects...
I would prefer not to rework the prototype boards I am submitting due to my misunderstanding...
Thanks!
--DickMS
"The CoinCraft A1 uses two SPI ports, one used in slave mode as an input from the uC or
the previous A1 in the chain (pins IN_MOSI, IN_MISO, IN_SCLK, IN_CS) and one in
master mode to the next A1 in the chain (pins OUT_MOSI, OUT_MISO, OUT_SCLK,
OUT_CS), if any."
In your pin descriptions, you use completely different signal names.
http://i.imgur.com/IXQavZw.png
http://i.imgur.com/tRFsGLK.png
It seems reasonable to assume that the above mentioned slave port, meant to be connected to the MCU or a preceding A1 consists of:
| Signal | Pin | Input to A1? |
| SCK_S | 13 | input |
| SDI_S | 14 | input |
| SDO_S | 15 | output |
| CS_I | 16 | input |
and the above mentioned Master port, meant to drive subsequent A1s consists of:
| Signal | Pin | Input to A1? |
| SCK_M | 8 | output |
| SDI_M | 7 | output |
| SDO_M | 6 | input |
| CS_O | 4 | output |
and that SPI signal flow outbound from the MCU will travel from right to left when looking down on a board with "pin" 1 in the upper left corner.
Could you please verify that I have the layout correctly described, please?
In addition, could you please verify the polarity of the chip select signals? Chip select is only rarely active high, and my controller is wired for the usual active low chip selects...
I would prefer not to rework the prototype boards I am submitting due to my misunderstanding...
Thanks!
--DickMS
October 29, 2013, 05:36:58 PM
Quote
Chip specifications, design documents, reference software, and everything that is required to design mining rig development will be provided through github incrementally, with a guaranteed availability of all required support material by end of October.
It is like 2 days away... And we are not even close to everything... We only have 1 thing that is close to useless...EDIT: sorry missed that it was chanced so not that useless but still missing a lot of promised staff...
October 28, 2013, 06:44:12 PM
I am assuming that the two drawings, the first in Section 5.1 labelled "Pinout", and the second on succeeding page labelled "Bottom View" are reversed because the first is actually a top view, right?
More questions, for Zefir:
These chips will be guaranteed operational, and tested before shipping, right? We can't act as your packaged-article test because we risk having to do rework on non-functional chips. There are no sockets for these chips for us to do the testing to reduce our risk, so perhaps they are tested at the factory after packaging, and that testing is covered in the pricing? Are the chips binned for voltage/frequency of operation (that is, are you guaranteeing all chips we buy will operate in Turbo mode, and produce 40GH/s there?) Are all 32 engines guaranteed operational? You can see where this is going... a guarantee of more free chips to make up for failed ones is not sufficient to make up for the rework costs, and system customers won't pay premium prices for boards with a chip that only partially works when it arrives.... Just want to know what we can expect to get our hands on... untested random gambles, or properly in-package-tested chips?
Thanks guy!
DickMS
More questions, for Zefir:
These chips will be guaranteed operational, and tested before shipping, right? We can't act as your packaged-article test because we risk having to do rework on non-functional chips. There are no sockets for these chips for us to do the testing to reduce our risk, so perhaps they are tested at the factory after packaging, and that testing is covered in the pricing? Are the chips binned for voltage/frequency of operation (that is, are you guaranteeing all chips we buy will operate in Turbo mode, and produce 40GH/s there?) Are all 32 engines guaranteed operational? You can see where this is going... a guarantee of more free chips to make up for failed ones is not sufficient to make up for the rework costs, and system customers won't pay premium prices for boards with a chip that only partially works when it arrives.... Just want to know what we can expect to get our hands on... untested random gambles, or properly in-package-tested chips?
Thanks guy!
DickMS
October 23, 2013, 08:11:12 AM
Can you provide more details on the package? You said it is a hybrid, but is the top exposed silicon?
Do you have any preliminary specs from the package manufacturer on expected Tjc for both the top and the bottom?
Thanks
Do you have any preliminary specs from the package manufacturer on expected Tjc for both the top and the bottom?
Thanks
October 21, 2013, 02:01:46 PM
Giorgio and other authors - there is a Wiki section on github too. I think most of the specs would be best hosted there, and the only thing that has to stay in a PDF is any mechanical drawings.
For all analog/signaling details, protocol description, etc - the wiki would probably work the best. And you can assign or give other people permissions to add content there which would further help with clarifying any specs details.
For all analog/signaling details, protocol description, etc - the wiki would probably work the best. And you can assign or give other people permissions to add content there which would further help with clarifying any specs details.
October 21, 2013, 10:09:09 AM
Still have no idea about CLKMUX and CLOCK pins.
October 21, 2013, 07:50:07 AM
Now it looks less friendly 
If I may suggest increase d0 dimmension and decrease b2 about 0.2mm. Extra GND track will fit there for decoupling capacitors, just like you did in the corners.
If I may suggest increase d0 dimmension and decrease b2 about 0.2mm. Extra GND track will fit there for decoupling capacitors, just like you did in the corners.
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