Topic: FPGA development board "Lancelot" - accept bitsteam developer's orders. - page 3. (Read 101887 times)

Thanks Kano for the additional info about that timings. Propably "long" will report very close to your calculations. After 12 hours U:5.8 (from 5.7), so it's little improvment, however hardware errors dropped to ~3% (previously was ~5%).
Yes luffy, resistors showed by rgzen are correct one.

@kano: many thanks, i will try it
@Dexter770221: can you please confirm the registors' location given by rgzen?
thanks

Don't forget that long (and short) depends on how idle the computer is.
long of course will keep correcting that forever, but short stops after a while and uses what it's worked out up to then.

The problem with both is that on a variable clock, it will sometimes be too long ... if the clock goes up by even 2%.
If you have a static clock then no issues, but you can then also use what's described below anyway.

However with a variable clock:

The fix is to actually specify the values.

It doesn't matter if they are a little out - that will only affect the MH/s reported ... as long as it's not too far out.

Try this instead:

--icarus-timing 2:70

2 (2ns) (Hs) means it clocks at 435MH/s (instead of 380MH/s) which just means that the MH/s reported will not be correct
1/(2x10^-9) H/s

70 (7.0s) (read_count) will be OK up to 613MH/s
(2^32/(70/10)) H/s

The issue of the '70' value is it MUST be less than the time it takes to check the full nonce range.
The closer it is to the correct time, the lower the overhead of getting more work.
That overhead is, however, very, very small.
It determines how much of each nonce range is checked (unless a share is found) but aborting early doesn't affect the probability of finding shares.
Normally the '70' (read_count) is calculated from the other Hs value
info->Hs = Hs / NANOSEC;
info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
info->read_count = (int)(info->fullnonce * TIME_FACTOR) - 1;
Hs=2 TIME_FACTOR=10 NANOSEC=10^9

The internal usage of the '2' value ensures correct MH/s display when a share isn't found.

P.S. I failed electrical engineering and got a Comp Sci degree

It is really a magic that all miners are electronic engineers

I've done it. Soldered 2x68k in serial on top of original 10k resistor. 1206 packages (I didn't have other values). Voltage jumped from 1.17V to 1.22V. So far so good but I don't see any big improvement... Results later.

v1 Lancelot (stock voltage) after 10 hours with --icarus-timing long i get better results:
A:3617 R:59 HW:92 U:5.5

That is why i plan to bump voltage on mines little bit more using potentiometer (Zetex voltmod  probably i will get 500K in parallel)
I will do it this weekend and will share the results  - i plan to bumop it around 1.28-1.29 < 1.30 just to be on a safe side as nghzang suggested:)

I have not notice much improvement without change the resistors. May be a 5 % or so...

5.63 seems like no improvment? What about utility before changing the res? Have you measured that?

Yes I measured before (1.178 and 1.181 aprox) and after (1.238 and 1.236 aprox).

And now it has 50 minutes running and it is at 5.63/m

Pls let us know what will happen with U 24 hours later. Have you measured Core voltage before/after changing resistors?

I have U: 6.6/m after 25 minutes, v1 with resistors changed.

I just wanna share my result so far...
All Lancelot's are v1 lower core voltage


 ICA  0:                | 758.9M/858.7Mh/s | A:2699 R:0 HW:71 U:  5.62/m
 ICA  1:                | 870.0M/888.8Mh/s | A:2822 R:1 HW:49 U:  5.87/m
 ICA  2:                | 884.2M/889.8Mh/s | A:2780 R:2 HW:26 U:  5.78/m
 ICA  3:                | 880.9M/874.2Mh/s | A:2757 R:0 HW:54 U:  5.74/m
 ICA  4:                | 865.6M/880.2Mh/s | A:2724 R:2 HW:52 U:  5.67/m
 ICA  5:                | 857.9M/876.1Mh/s | A:2748 R:0 HW:35 U:  5.72/m
 ICA  6:                | 873.7M/865.3Mh/s | A:2777 R:0 HW:56 U:  5.78/m
 ICA  7:                | 857.5M/867.4Mh/s | A:2735 R:0 HW:34 U:  5.69/m
 ICA  8:                | 866.8M/866.5Mh/s | A:2790 R:0 HW:54 U:  5.80/m
 ICA  9:                | 708.7M/861.4Mh/s | A:2698 R:0 HW:43 U:  5.61/m
 ICA 10:                | 880.1M/874.1Mh/s | A:2736 R:0 HW:70 U:  5.69/m


Average utilization with stock v3 bitstream was about 5.2 - 5.3 which is about 10% improvement
My next step will be to bump up core voltage to 1.26 as suggested and i will share results..
Nghzang,
Can we bump input voltage a little bit more? Is it safe to stay below 1.3 V as you suggested. Probably 1.295 IDLE will be even better instead of 1.24?

i am not sure but i guess the final batch since Lancelot was already announced
to avoid misunderstandings, i haven't flashed Icarus. It is using the default bitstream.

If someone is in Hong Kong or can donate a "Lancelot"  I can take a look at this and do a tutorial, including an idiots guide to loading/flashing the bitstream, possibly WITHOUT using the ISE.
Then I can sit down and run a set of bench marks.

I'm just sat about waiting for delivery of ASIC boards/ Stock trading, so I need a project to keep me busy.

HC

Sir, can you please tell me which version of bitstream your icarus is using ?  V3 or which one ?

Assuming it doesn't die, the U value will begin to converge on the expected average after a few days ... on a 1 diff pool.

U: 5.7 after 1 hour.

you should check only the Utility (U:) . my icarus has 5.2 but lancelot with new bitstream 4.9, thus old bitstream is
better. i will see if i can solder new registors, i guess v1 is the board that is shown in the very first picture of this thread
by ngzhang  

Oh. So good ?!

Pity that my board is icarus bought from xiangfu. Could not utilize the powerful update.