Topic: GekkoScience BM1384 Project Development Discussion - page 38. (Read 146665 times)

Don't worry, I have a pretty good stress management mechanism called "shrugging it off". I do what I can to solve the problem, but when it's out of my hands I stop worrying about it. So if we don't have a pick-and-place by the time parts arrive I'll be assembling sticks by hand to get it done, because that's what I can do, but in the meantime all I really have is complaining and that doesn't really take a toll on any of my gaskets.

I got burned by BFL to the tune of one Jalapeno, which I ended up forcing a PayPal refund after four months of non-delivery, used it to buy an AM Blade, and within three months had turned related products and services, and reinvested mining revenues, into 300GH of gear. All in all I call it a win. Given the only other time I've "preordered" hardware was a pair of X-1 from Minersource, which I last July traded off for a pair of Technobit Minion boards that have yet to appear (only $800 spent seventeen months ago with nothing to show for it), I'm more upset (on my own account) at bobsag3 and Marto than I am BFL but on the whole BFL are the bigger villains.

I got burned by BFL to the tune of ~$4,000.

I hate the hassle and delays of importation. Dealing with companies that are not subject to the laws of the destination country is bogus.

Please don't blow a gasket in the heat over the P'n'P we need you too much (selfish little bastards aren't we).

Your call on the thread.
I have 0 experience moderator - ing.

Simply stated, if the community (of which I'd like to think we're a part) designs the chip, then the community owns the design (all the stuff one forwards to a foundry to get a run made). Put it up on GitHub. GPL licensed open source hardware? In theory, anyone could take that design and have a foundry make'm a batch. Much like an individual D/L's source compiles it and runs it. Given H/W is a little different as most can't afford a "foundry compiler" but a group might be able to pool resources and have a run made. And this community has pulled together in the past to make things happen.

Our primary goal is to facilitate the availability to the community (big and small, whomever) a ready supply of high quality state-of-the-art raw materials regardless of whom the seller may be. Might be us, might be Gekkoscience, might be Bitmain, might be Bob & Ted's Really Cool Chip Company, might be a group buy, etc. . . . . . Because in the past and present a slim few have controlled the flow of raw materials. Kinda' like DeBeer's does with diamonds. Throttling the volume to maintain an artificially inflated price. The business rationalization is "We paid for the design, it belongs to us, we're the only game in town, and we'll charge what the market will bear." Even the playing field, and that model collapses.

With an even playing field, margins will be what margins will be. Typically, the larger the field the smaller the margins. If we expand the playing field, margins will take care of themselves.

As an example, I offer what happened to PC's. In the early 80's IBM was the only supplier. In 1981 an IBM 5150 PC with two 360K floppies was $25,000 (from IBM's Entry Level Systems Division). By the late 80's there was a plethora of brands/suppliers (I bought a Kaypro in 86 during this era) and the price had dropped to $1200 with a 20meg MFM HD (IBM PCXT clone). With a little brains one could buy the parts and assemble one themselves for less than $1000.

So as long as hash chips remain propriety they'll be priced outta' this world. Standardize the design and . . . .
I think this is an achievable goal given the industry has bumped into the 12-14nm concrete wall, SHA-256 circuitry is about as optimized as it can get, and fabricating ASIC's is common place.
Let the community set the standard not corporations.

Yeah, those three are the ones I could think off offhand and am not particularly fond of any of them. The two that went overtly bankrupt after screwing customers both also built chips in form-factor I despise, and the third that somehow avoided getting thrown in jail should be thrown in jail despite actually eventually coming up with decent gear, so not really too impressive a showing. I'm biased toward US companies because I sorta am one, and there are a whole lot of miners in the US that can only buy imported gear which sucks. That we can only import sucks, not necessarily the gear. Some of it's alright.

Heatsinks for the Compac batch are on order, and probably about that color green. PCBs are also on order. It took a bit longer to get them out because we were discussing what we wanted for panelling and stencils and such.

We're also still having trouble convincing the mother@!#$ pick-and-place manufacturer to actually solve the @!#$ problem and get us our @!#$ machine. We expected delivery actually slightly earlier than they ended up shipping it. We've asked if they'll ship us another unit so we don't get screwed while they work out how to get their returned unit back from DHL, but they'd apparently rather not actually meet customer needs. Which of course the whole thing would have been avoided if some jackass in shipping wasn't too lazy to copy-paste our phone number into the order details - which some less-lazy jackass in shipping specifically asked us for exactly to avoid what's happening now - so US Customs would have actually known who to talk to so it could be cleared. Not happy about that. So, it's entirely possible Compac delivery will be delayed because a problem whose solution was provided IN ADVANCE SEVEN WEEKS AGO happened anyway and has yet to be resolved.

Meanwhile, well, I reckon we'll continue to work on multi-chip designs and Compac driver support. I'll be honest though, the heat index right now is 105F so there's probably not much gonna get done that doesn't get done between 7AM and noon this week.

Entirely rhetorical, I know, but for chips I think it's only been 3? BFL, CoinTerra , HashFast.  Not counting the ones that failed to launch, only have private claims (21, Inc.), or are U.S. registered (among other) mostly for presence sake.

On the bright side - the U.S. isn't alone in companies having come and gone.  Just look how few are left over from the Asian market compared to how many there have been.  Same for Europe.  It just tends to blow up more when it's U.S. companies in part due to the legal system and the media coverage.

In case this does get split off to a new thread: good luck, regardless

---

In terms of this thread - I spent the better part of the afternoon salvaging valuables off of computers to be decommissioned at work, and found a nice heat sink that was on a ... well, not sure actually.. some VIA chipset anyway from a 2004-era machine.  Looks like this, minus the wings.

So I can cut that down to size some and stick it to the back of my 'engineering sample', give it a bit of (GekkoScience) green after all

Yeah, a fair bit of discussion lately has shifted away from our BM1384 designs. Should we start a new thread just for chip design ideas? I have no complaints about the thread so far, but it might be handy to keep track of things better if we're not bouncng between two or three different conversations.

I'm all in favor of an American chip supplier - one that's not going to screw everyone over and/or go bankrupt, at least. I mean we've already seen how many US manufacturers come and go in the last couple years? If we can keep the intention fairly community-based instead of single point greed like a lot of the big guys, margins might be slim but a whole lot of people would benefit. If PlanetCrypto is already figuring out how to do the heavy lifting, I'm certainly going to do what I can to help.

In brief, this is what (a supplier) we (PlanetCrypto or a spin off LLC) are seriously investigating.
I'll be the first to admit that chip design is not a skill set I possess. In fact, one might say I'm clueless in that regard.
I do know that it is a skill set that can be learned, acquired, and worst case bought and with the guidance and brilliance available here I believe it's a doable thing.
I also believe that with a looming block reward decrease and serious talks about increasing block size to 20 Mb, little miners are doomed.
http://www.cnbc.com/2015/07/23/bitcoins-war-could-threaten-its-survival.html
This is not something that I believe is a healthy direction for the Bitcoin ecosystem to travel down. But WTF do I know anyway.

Since none of the "big 4" chip makers have any decent chips/boards/miners available, an opportunity to fulfill that need exists.
And if we're gonna "take the plunge" I'm in favor of "doing it right".

Will we get a chip to tape out?
Only time will tell.
But since no one else seems to be pursuing it, we're gonna' give it a shot.
If we fail to tape out a hash chip then at least the "brain working" will be completed for a "next gen" hash chip that another entity could "pick up the ball and run with".

For us as a company the timing is synergistic as we have 2 other chip designs in the conceptual stage of development.
We own some of the physical assets necessary (a small computing farm most notably) to get through the design/simulation process.
Our current plan is to concentrate on the hash chip first because it's the most time constrained and in the "dead spots" of getting that chip to tape out move forward on the other 2 designs.

And at the risk of alienating potential participants, I also believe it's about time for an American supplier (who is the antithesis of BFL) to enter the mix.

Not trying to be caustic, just figured we'd justify/clarify why we're cluttering up sidehack's thread.

Agreed! So many great minds in this community

It is so refreshing to see conversations like this in hardware now.  No flaming, no trolling just an honest exchange of ideas.  Keep it up gents.  Some of us may not be adding to the discussion but we are intently reading it. 

I'm going with the 5 lead in 1 month, given the rate at which designs become obsolete in the BTC ecosystem.

"With a 10x10mm you could probably go 12-15W without a lot of problems, thinking from a chip-level power density scale (though it would depend on actual die size and Tjc) - if we're comfortable with 10W from an 8x8, 10x10 has 1.56 times the surface area for heat transfer."

Couple of reasons I like 10W:
1) Like to try to be conservative for longevity's sake.
2) Overclockers (like me) will push a design way past factory recommendations.

There probably is a better way to do it, just me being ignorant.

Isense resistance in bucks is, from my experience, in the mOhms. On/in chip, I think that can be dropped 1 or 2 (maybe 3) orders of magnitude resistance and if necessary use a more sensitive higher precision A/D say a 12 - 14 - 16 bit A/D versus an 8 or 10 bit.


Yes, and with an internal RTD one could throw Tj into the calculation mix as well.
I'm sure I'm not the only one who has observed the hash rate drop as a unit heats up.
If one can control the Vcore and clock one might be able to mitigate this effect and re-fine tune it for changing ambient conditions.
Additionally, it would, like some CPU's do, allow a sliding scale of operation.
Protecting the chip from damage while allowing reduced capacity operation.
As opposed to say the Bitmain S(odd) which when it hits the magical 80C stops entirely.

Perfect for whom?
Bitcoin miners?


F'ing brilliant, have worked with 3 phase motor controllers that were 15 pin packages (if memory serves). Just trying to envision what the chip/heatsink/board combo would look like.


In the Synopsys world of IP things these SHA-256 cells are a proven item down to 14nm. I assume that they have taken that into account (... noise margins for each gate/transistor).


First off I've worked more with SPI, so I'm biased in that direction. My gut feeling is that SDLC/HDLC/LAPB et.al seems like overkill from a protocol perspective. Probably am FUBAR. Obviously I need to take a second look.

Exactly my thought. Was thinking an external clock feeding an adjustable internal PLL clock divider. In/on multiple chip boards one common external clock feeding multiple chips. That clock input could be configured on a chip by chip basis based on a writable register setting. Thereby allowing each chip on the board to be clocked differently.

Makes perfect sense.

This is a snippet of info I was totally unaware of. Thanks. Typically, do these clock generators "slide" the freq up and down or are they selecting a predetermined freq from a pool of freqs and then hopping amongst them?


That sounds dreamily expensive, if for no other reason than it has the word "Intel" in it. lol

Ah, confused by imprecise terminology. A shunt current measurement, yeah that could be handy. However, any resistive power loss is going to affect overall performance. A 10W device at 0.7V runs 14A, so you lose 2% per mOhm shunt resistance unless there's a better way to do it?

With internal PLL and the ability to send commands to individual chips, it would be possible to set individual chip clocks. If you could also measure voltage and current per chip, that could also be used to help balance and stabilize strings.

My thought was to build in the ability to sense individual chip current draw and knowing Vcore yields chip W consumption, which is a component of W/GH/s. This combined with a knowledge of clock freq would provide the data to fine tune individual chips for most economic operating point.

I envision this value would be stored in a register on chip and externally read only. The voltage off the shunt feed to a simple A/D (8 or 10 bit) sampled every 100ms might suffice.

1) Dunno. I'd probably start looking at a different seven-lead package because it'd be easier for me to retool mechanical than retool both silicon and software, especially if I had to retool mechanical for a package change anyway.

2) I also prefer star over chain for comms. I'm not so worried about clocked vs async so much as addressing, chip-select, collisions and whatnot. I kinda like how ASICMiner does it, with individual chip-selects for work distribution and polling from a single controller. If timeouts for work completion polling and queueing aren't done up right you can lose some marginal time efficiency but all that should be pretty easy to keep track of. You also don't get the problem of one chip bailing and taking out everything downstream - which, as you mentioned, is a definite risk. Daisychaining comms on a basic protocol makes it easy to run a board without a micro, but it's probably worth the extra complexity for the massive increase in overall reliability.

I'm not in favor either. But I understand the constraints of the lead time. If you had a choice of your ICs delivered in 5-lead packages in 1 month or in 7-lead packages in 6 months, which one would you choose?

I see this question as incorrectly posed. There are actually two independent choices in it:

1) UART vs SPI. On this I have no real preference, but way more experience with USARTs (that includes not only asynchronous but also synchronous devices/protocols.). Even the very lame UARTs have parity error detection, whereas very lame SPIs have nothing but "Hail Mary" protection.
2) Star topology vs daisy-chain topology. On this I prefer star because the ICs need to be running at the edge of failure (thermal or noise), otherwise the project is not competitive.

Yep. Like I said in that other thread, if we started a fight over who's the better engineer I'd probably lose. Why not pay attention to the advice of someone with more experience in the particular field being discussed?

Course, being as I do work at the product level I have to consider the ease of manufacture, which single boards are a heck of a lot easier to work with than ribbon cables on the assembly line. Embarassingly parallelizable works in two dimensions but if you need orthogonal planes for things it starts to make things interesting.
If 10W range is what you get with non-custom ready packaging, it makes me like 10W range that much more.

I am not in favor of one-wire communication. No real reason to make both endpoints more complex in order to save a couple traces/leads.

What are your thoughts on the previous discussions regarding chained UART versus address-decoded SPI?

Thank you very much. I was hoping that you can take my comments not as a challenge, but as a simple exchange of ideas. Your experience seems to be complementary to mine, as I know more, and did more, of the inside-the-IC design as opposed to the general circuit/product level.

You need to stop thinking of "boards" and "large flat surfaces" as a necessary or desired property. We aren't designing a computer or anything like it. This is an problem in the class "embarrassingly parallelizable". Think of a series of very small boards electrically connected with two ribbons: one thick for power, one much thinner for signaling. The mechanical strength of the design will be provided by screwing the packaged chips to the large rail of aluminum heathsink. Or wrapping the chips around steel cylinder of one-stage water cooling loop.

My idea of minimum pinout:

0) common ground on the heathsink
1) Vcore/analog
2) Vglue/digital
3) ClkCore
4) ClkGlue
5) RxD
6) TxD
7) Reset

When push comes to shove the last three could be rolled into one using some 1-wire communication protocol. Obviously Vcore/analog would carry the most current and the most power so it will become a limit when using non-custom packaging. So it will be more like 50*10W with non-custom fast-turnaround packages or 10*50W or even 2*250W with customized high-current slow-turnaround packaging (similar to e.g. https://en.wikipedia.org/wiki/Silicon-controlled_rectifier ).



I found better pictures under https://en.wikipedia.org/wiki/Thyristor

I have hated BGA since all this BS with the xbox and ps3 systems. Hell laptops and video cards have the same issue but not as bad as the game consoles have had. I am surprised not many issues have popped up so far with the fact some of these mining machines using BGA run 24/7 for weeks on end and get pretty warm. But then again hardware usually gets less and less efficient every month and usually is squeezed out about 6 months after unless you mod/tune it. But there are people like me and mine till she blows or buys a new toy.