Any thoughts about possibly being first to market with a USB 3, miner?
Topic: GekkoScience BM1384 Project Development Discussion - page 41. (Read 146713 times)
I wonder how hard it'd be to integrate level shifting for string comms? Something like an absolute ground pin and your SPI comms and clock feed in at that ground, then internal circuitry shifts it up to local ground reference. A good high-speed opamp referenced to absolute ground could take care of a lot of that by simply summing the incoming data with local ground. I wouldn't be surprised if someone came up with a better way to do it, that's just the first that came to mind. Clock would be a bit harder since you'd need a high GBP amplifier, or you could use a DC blocking cap and resistor divider to re-bias at local ground - that's what I'm using on my BM1384 test strings with good results. Integrated level shifters like that would simplify string design a fair amount.
The nice thing about UART is that you can have async plugging of devices, unlike SPI that isn't compatible with that kind of scenario (for some weird reason).
Although you could have an out of band indicator that triggered a SPI rescan, but that would be departing too much from the ultra simple protocol.
Although you could have an out of band indicator that triggered a SPI rescan, but that would be departing too much from the ultra simple protocol.
Oh man, I'd love to work with a QFP-EP miner ASIC. You'd probably see a lot of DIY and third-party designs pop up if there was good chip data available - original BitFury and BE200 kind of cultures. Using a basic comm protocol like SPI or UART would make dev super easy (not like, you know, a custom protocol implemented in an FPGA or something). I'm a fan of UART, but Novak seems to like SPI. SPI certainly has the advantage if you're doing parallel comms because of the hardware select lines instead of requring addresses in the protocol. Requires decoder hardware but that's a nothing problem.
I was thinking about ethernet working around collisions in the mid 70's but that's because I don't know WWII radio relay history. Nice tidbit of knowledge I'll have to look up now.
I was thinking about ethernet working around collisions in the mid 70's but that's because I don't know WWII radio relay history. Nice tidbit of knowledge I'll have to look up now.
Thanks guys, this is the stuff I need to hear.
Our other projects (non crypto currency) are low power devices (or will be). They'll need to rad hardened cuz' of what we're gonna engineer inside the carrier. nuff' said.
Was digging around on the Synopsys website, seems they have pre-engineered SHA-256 cells in their IP library (amongst other cool stuff).
Am leaning towards QFP-EP design. I like contacts I can see. But I like the option of through PCB heat dissipation and a solid GP.
Seems QFP-EP starts @ 10 mm3 and goes up from there. So 8x8 is doable.
Like the idea of parallel I/O and stick a brain dead MC on the board for internal/external comms. Also want a the small MC for some refinements (core clock, per chip temp monitoring, per chip power consumption monitoring, hash rate monitoring, work unit buffering, NVRam, etc. . .)
"... but simple collision-resolution protocols for shared IO lines have been around since forever" Radio Talkers in WWII (CSMA/CD) is where ethernet came from. What's old is new again.
Gotta' get to bed so I can pay attention to tomorrow.
L8r folks.
Our other projects (non crypto currency) are low power devices (or will be). They'll need to rad hardened cuz' of what we're gonna engineer inside the carrier. nuff' said.
Was digging around on the Synopsys website, seems they have pre-engineered SHA-256 cells in their IP library (amongst other cool stuff).
Am leaning towards QFP-EP design. I like contacts I can see. But I like the option of through PCB heat dissipation and a solid GP.
Seems QFP-EP starts @ 10 mm3 and goes up from there. So 8x8 is doable.
Like the idea of parallel I/O and stick a brain dead MC on the board for internal/external comms. Also want a the small MC for some refinements (core clock, per chip temp monitoring, per chip power consumption monitoring, hash rate monitoring, work unit buffering, NVRam, etc. . .)
"... but simple collision-resolution protocols for shared IO lines have been around since forever" Radio Talkers in WWII (CSMA/CD) is where ethernet came from. What's old is new again.
Gotta' get to bed so I can pay attention to tomorrow.
L8r folks.
[...]
If I were designing a mining ASIC I'd probably try to make something in the 8x8-10x10mm QFP neighborhood, typical peak consumption about 10W, with a single belly pad. If possible use one full side of pins for Vcore. I'll have to think about comms, because I've seen chained and common-line (parallel) all work. Probably go with a parallel IO (like ASICMiner uses) because it's more fault-tolerant of chips bailing out. With chained comms (like Bitmain uses), if you kill one chip every chip downstream of it loses connection because each chip acts as a relay. That is handy for traffic control because there really aren't any collisions, but simple collision-resolution protocols for shared IO lines have been around since forever, and there's always sequential polling either with addressing or individual select lines. Requiring board-level address decoding for comms to work increases the board-level requirements over chained comms, but with a good IO chip it shouldn't be too bad to implement (as many ASICMiner-based designs have proven). For string topology the node-level signal level shifters would be a bit more intensive with a common IO line than with chained comms, but the only thing to really worry about would probably be the core clock. Integrated temp monitoring sure would be nice too.
If I were designing a mining ASIC I'd probably try to make something in the 8x8-10x10mm QFP neighborhood, typical peak consumption about 10W, with a single belly pad. If possible use one full side of pins for Vcore. I'll have to think about comms, because I've seen chained and common-line (parallel) all work. Probably go with a parallel IO (like ASICMiner uses) because it's more fault-tolerant of chips bailing out. With chained comms (like Bitmain uses), if you kill one chip every chip downstream of it loses connection because each chip acts as a relay. That is handy for traffic control because there really aren't any collisions, but simple collision-resolution protocols for shared IO lines have been around since forever, and there's always sequential polling either with addressing or individual select lines. Requiring board-level address decoding for comms to work increases the board-level requirements over chained comms, but with a good IO chip it shouldn't be too bad to implement (as many ASICMiner-based designs have proven). For string topology the node-level signal level shifters would be a bit more intensive with a common IO line than with chained comms, but the only thing to really worry about would probably be the core clock. Integrated temp monitoring sure would be nice too.
QFP mining chip would be amazing... and some protocol like SPI would kick ass... even better, find out a protocol that allows hot-pluggin of expansion boards, that would be great.
As i said in the other thread, a DIP miner chip would be a dream come true... but i doubt there's lot of interest on this kind of development in an age were everthing is an IP core for an asic
QFN is acceptable, but being the comparatively low-tech shop we are, a larger than 0.5mm pitch is preferred and things with pins are greatly preferred. Being able to see what you're doing makes doing it a lot easier, and QFP allows that. I don't know what the technical term is for the cross-section of the pad which is exposed on the edge of the chip, but if there's enough of that to make visible verification of at least the edge pads possible is nice.
I would tend to prefer chips in the max-15W range like BE200, BM1384 and such. Going hotter than that (Avalon A3222) can greatly increase local cooling requirements, unless the chip has a lot more area (like the A1). I'd prefer to avoid BGA for the aforementioned difficulties in routing and installation, as well as power density. Not many really stable machines have been run out on power-dense BGA chips, that weren't greatly assisted by expensive or complex watercooling systems (which I would also prefer to avoid). Immersion cooling is a big help, as PlanetCrypto likes to remind us (and he's done some pretty cool stuff with it), but most people have a lot more air in their homes than Novec or mineral oil so I'd prefer to stick to things capable of native air-cooling. It may not be the best option for everyone but it's an option literally everyone can work with.
If I were designing a mining ASIC I'd probably try to make something in the 8x8-10x10mm QFP neighborhood, typical peak consumption about 10W, with a single belly pad. If possible use one full side of pins for Vcore. I'll have to think about comms, because I've seen chained and common-line (parallel) all work. Probably go with a parallel IO (like ASICMiner uses) because it's more fault-tolerant of chips bailing out. With chained comms (like Bitmain uses), if you kill one chip every chip downstream of it loses connection because each chip acts as a relay. That is handy for traffic control because there really aren't any collisions, but simple collision-resolution protocols for shared IO lines have been around since forever, and there's always sequential polling either with addressing or individual select lines. Requiring board-level address decoding for comms to work increases the board-level requirements over chained comms, but with a good IO chip it shouldn't be too bad to implement (as many ASICMiner-based designs have proven). For string topology the node-level signal level shifters would be a bit more intensive with a common IO line than with chained comms, but the only thing to really worry about would probably be the core clock. Integrated temp monitoring sure would be nice too.
I would tend to prefer chips in the max-15W range like BE200, BM1384 and such. Going hotter than that (Avalon A3222) can greatly increase local cooling requirements, unless the chip has a lot more area (like the A1). I'd prefer to avoid BGA for the aforementioned difficulties in routing and installation, as well as power density. Not many really stable machines have been run out on power-dense BGA chips, that weren't greatly assisted by expensive or complex watercooling systems (which I would also prefer to avoid). Immersion cooling is a big help, as PlanetCrypto likes to remind us (and he's done some pretty cool stuff with it), but most people have a lot more air in their homes than Novec or mineral oil so I'd prefer to stick to things capable of native air-cooling. It may not be the best option for everyone but it's an option literally everyone can work with.
If I were designing a mining ASIC I'd probably try to make something in the 8x8-10x10mm QFP neighborhood, typical peak consumption about 10W, with a single belly pad. If possible use one full side of pins for Vcore. I'll have to think about comms, because I've seen chained and common-line (parallel) all work. Probably go with a parallel IO (like ASICMiner uses) because it's more fault-tolerant of chips bailing out. With chained comms (like Bitmain uses), if you kill one chip every chip downstream of it loses connection because each chip acts as a relay. That is handy for traffic control because there really aren't any collisions, but simple collision-resolution protocols for shared IO lines have been around since forever, and there's always sequential polling either with addressing or individual select lines. Requiring board-level address decoding for comms to work increases the board-level requirements over chained comms, but with a good IO chip it shouldn't be too bad to implement (as many ASICMiner-based designs have proven). For string topology the node-level signal level shifters would be a bit more intensive with a common IO line than with chained comms, but the only thing to really worry about would probably be the core clock. Integrated temp monitoring sure would be nice too.
What package types do you prefer to work with (i.e. are easiest to work with)?
not-sidehack here, but he's mentioned a few details before:
If it was BGA I wouldn't be messing with it. The QFN is bad enough by itself. I wish this chip had a larger cross-section of pad at the edge, which would make checking solder jobs better because it'd wrap around a bit.
I concur.
Basically, does it have actual leads (e.g. TSSOP, QFP, etc.)? Awesome - dead-simple to solder, even down to fairly fine pitches, even hobbyists can work with this and a rusty old soldering iron.
Doesn't have any leads out, but at least they go to the side of the package (e.g. QFN)? Still pretty doable.. plenty of soldering surface and easy to inspect, benefits from some SMD experience but decent soldering iron will still do the trick.
Doesn't have any leads out, and they barely go to the side of the package or not at all (e.g. LPCC)? Starting to get problematic, depending on exact geometry, it becomes difficult to gauge whether solder connections are solid.
( note: the BM1384 suffers from this a bit - instead of a single exposed pad, it has multiple for power - but they're fairly large so not too bad )
Is it a (fine pitch - which they all tend to be) BGA? Now you're going to need dedicated equipment.
Is it an LGA? Good luck. with that.
Depending on what you're designing, I'd at least try to target QFN, and try to stay away from the crazy custom pads unless advantageous
We have other concepts/projects we're working on that are not in the BTC realm but will ultimately be chip based. Consequently, we're slowly gearing up to design our own propriety chips.
What package types do you prefer to work with (i.e. are easiest to work with)?
What package types do you prefer to work with (i.e. are easiest to work with)?
QFN, even with crazy custom pads (a-la the A1) is just fine!
-a[g
If the connection isn't perfect, which can be really hard to determine when you have to check 400 connections all of which are sandwiched between two boards (so, X-ray), gotta bake it back into shape. If balls fail you need templates and fresh balls to re-ball the chips. Oh also routing sucks when you have to tie signal lines around inside a matrix of several hundred vias.
Using ionizing radiation (x-ray) brings it's own set of issues to semiconductors. Just talk to the guys that designed semiconductor control circuits for the first nuc weapons. And the expense/hassle of getting licensed to operate an industrial strength x-ray emitter.
Unless the footprint and pinout and protocol for successive generations of chips is the same (which is highly unlikely), building a board with sockets would be great for adding expense and slightly increasing the ease of manufacturing but not necessarily make a better end product. And it still doesn't solve the problem of me not wanting to design a couple-hundred-amp multiphase regulator and worry about high-power-density cooling concerns when, in my opinion, that design concept is just about the worst available. Remember, we like simple and efficient and the inherent reliability simplicity and efficiency help bring to the table.
"Unless the footprint and pinout and protocol for successive generations of chips is the same ..." And is a contributing rationalization for getting into designing/implementing chips.
"... design a couple-hundred-amp multiphase regulator ..." = serious PITA.
"... and worry about" board level "high-power-density cooling concerns ..." in addition to chip heat dissipation issues.
"... simple and efficient and the inherent reliability simplicity and efficiency help bring to the table." KISS is always preferred.
The only way to make it worse worse is to greatly increase the required power without substantially increasing the die size available for cooling - so, like Hashfast chip instead of Spondoolies chip. The only reason SP's Rockerbox gear works as well as it does (which, by the way, it doesn't really work for crap if your ambient is over about 30C) is because the chips themselves are built like tanks and handle 120C. As much as I may conceptually dislike SP gear, their chip design design guys are quite skilled and I'm impressed at what their machines can do given the limitations their design concept imposes on efficiency.
"... greatly increase the required power without substantially increasing the die size available for cooling ..." Which is probably why they were playing around with immersion cooling. i.e. larger BTU per mm2 than air can dissipate.
Well, one doesn't know till one asks, thanks.
We have other concepts/projects we're working on that are not in the BTC realm but will ultimately be chip based. Consequently, we're slowly gearing up to design our own propriety chips.
What package types do you prefer to work with (i.e. are easiest to work with)?
It was mentioned in the review thread, guess I forgot to say something here.
https://bitcointalksearch.org/topic/run-2-closedsidehack-stickgekkoscience-compac-official-sales-thread-1126705
Sales open in 22 hours, limit 10 per customer without previous arrangement.
https://bitcointalksearch.org/topic/run-2-closedsidehack-stickgekkoscience-compac-official-sales-thread-1126705
Sales open in 22 hours, limit 10 per customer without previous arrangement.
I was out of town for a few days and wanted to be sure I didn't miss the "on sale" announcement? I don't see mention of it in this thread, but just wanted to double check. Thanks.
Yeah, that's very pragmatic, and that's what get results, so better stick to those principles and get some hardware out there 
I wouldn't mind the challenge (learning experiences and all), but I would mind what could be seen as a waste of resources when I'm better equipped to pull off a more efficient machine in substantially less time with the tools I already have. Someone else could do a big BGA chip build better than I could in less time.
If the connection isn't perfect, which can be really hard to determine when you have to check 400 connections all of which are sandwiched between two boards (so, X-ray), gotta bake it back into shape. If balls fail you need templates and fresh balls to re-ball the chips. Oh also routing sucks when you have to tie signal lines around inside a matrix of several hundred vias.
Add to that RF issues generated by that web of routes and you have a nice 5-6 months of debugging and hair pulling.
If the connection isn't perfect, which can be really hard to determine when you have to check 400 connections all of which are sandwiched between two boards (so, X-ray), gotta bake it back into shape. If balls fail you need templates and fresh balls to re-ball the chips. Oh also routing sucks when you have to tie signal lines around inside a matrix of several hundred vias.
Unless the footprint and pinout and protocol for successive generations of chips is the same (which is highly unlikely), building a board with sockets would be great for adding expense and slightly increasing the ease of manufacturing but not necessarily make a better end product. And it still doesn't solve the problem of me not wanting to design a couple-hundred-amp multiphase regulator and worry about high-power-density cooling concerns when, in my opinion, that design concept is just about the worst available. Remember, we like simple and efficient and the inherent reliability simplicity and efficiency help bring to the table.
The only way to make it worse worse is to greatly increase the required power without substantially increasing the die size available for cooling - so, like Hashfast chip instead of Spondoolies chip. The only reason SP's Rockerbox gear works as well as it does (which, by the way, it doesn't really work for crap if your ambient is over about 30C) is because the chips themselves are built like tanks and handle 120C. As much as I may conceptually dislike SP gear, their chip design design guys are quite skilled and I'm impressed at what their machines can do given the limitations their design concept imposes on efficiency.
Unless the footprint and pinout and protocol for successive generations of chips is the same (which is highly unlikely), building a board with sockets would be great for adding expense and slightly increasing the ease of manufacturing but not necessarily make a better end product. And it still doesn't solve the problem of me not wanting to design a couple-hundred-amp multiphase regulator and worry about high-power-density cooling concerns when, in my opinion, that design concept is just about the worst available. Remember, we like simple and efficient and the inherent reliability simplicity and efficiency help bring to the table.
The only way to make it worse worse is to greatly increase the required power without substantially increasing the die size available for cooling - so, like Hashfast chip instead of Spondoolies chip. The only reason SP's Rockerbox gear works as well as it does (which, by the way, it doesn't really work for crap if your ambient is over about 30C) is because the chips themselves are built like tanks and handle 120C. As much as I may conceptually dislike SP gear, their chip design design guys are quite skilled and I'm impressed at what their machines can do given the limitations their design concept imposes on efficiency.
"Some new equipment" being everything required to work with BGA properly. Balling gear, probably some good IR reflow stations with preheat trays, stuff like that.
Military trained me in 2M on a Pace 2500 in the early 80's. So have a handle on IR reflow and the trays. Have any specific manufacturers and models in mind?
I have 0 experience in BGA. WTF is "Balling gear"? Thought BGA chips had the little balls built into them. Think I've seen (Digikey?) BGA sockets like Intel uses for CPU's.
Just thinking outloud here:
1) If BGA sockets are available,
2) and a board with multiple sockets (say 4+) could be designed,
3) then, in theory, one could purchase a board and a hash chip (Spondoolie) and be up and running,
4) one could then buy additional hash chips and "grow" in hash power as desired.
I get that the sockets would add additional expense to the initial board cost, but would add the flexibility to cover multiple purchasers needs.
Maybe if one bought the sockets in bulk one could drive the cost down a tad.
"Some new equipment" being everything required to work with BGA properly. Balling gear, probably some good IR reflow stations with preheat trays, stuff like that.
I don't think you understand. What we intend to do is built it well enough that it won't break or fail, and then sell it such that you can actually turn a profit. If the only way to build it good enough to meet our standards is to make it so expensive it's not worth buying, we'd rather not build it at all. We'd rather not get sales than sell something we don't think is good enough to basically put on a lifetime warranty. If I've built it well enough, it would be the customer's fault it catches on fire - something about cranking it to maximum power, taking off the fan and then stuffing it under a couch cushion.
If I built something like the Dice I'd use a matrix of more manageable chips instead. Unless you wanted to pay me at least $500 a week and sponsor some new equipment for the dev, I ain't messing with Spondoolies chips.
The Avalon nano is easy to improve on, since it was built with their previous-gen chip. I expect them to have a next-gen chip in a month or two that I'll probably take a look at.
Also, the shipping yard is in China so we can't really just drive there. I'd rather have the machinery than the money back, because if I got the money back I'd just spend it on the machinery again and that would probably mean paying the $750 shipping fee again, which ain't gonna happen.
If I built something like the Dice I'd use a matrix of more manageable chips instead. Unless you wanted to pay me at least $500 a week and sponsor some new equipment for the dev, I ain't messing with Spondoolies chips.
The Avalon nano is easy to improve on, since it was built with their previous-gen chip. I expect them to have a next-gen chip in a month or two that I'll probably take a look at.
Also, the shipping yard is in China so we can't really just drive there. I'd rather have the machinery than the money back, because if I got the money back I'd just spend it on the machinery again and that would probably mean paying the $750 shipping fee again, which ain't gonna happen.
"... some new equipment for the dev,"
Like what equipment?
Ohm's Law sucks sometimes. 100W / .5V = 200A. Hhhhmmmmm, so circuit traces made out of #2 welding cable? LOL, wonderful mental image.
"... - something about cranking it to maximum power, taking off the fan and then stuffing it under a couch cushion."
I would pay good money to be a fly on the wall . . . but only if the user sat on the cushion. LOL
"... and it would be very difficult for me to care less than I already do about scrypt."
ROTFL, I'll think about this off an on all day tomorrow and snicker uncontrollably.
Every international shipment we've done that's >$2499 has been a customs nightmare.
For what little it's worth, my heart goes out to you.
Also. I spent a bit of time talking with Novak about the most badass things to make miners shaped like. His suggestions were mostly aerospace-related (which makes sense), like the J58 engine housing from an SR-71, or a F1 engine from the Saturn V rocket. Unfortunately those things aren't exactly rectangular.
So we're gonna proceed with making something look like a big V8. I'm working on an idea for a supercharger with internal fans as the air intake for the topside heatsink. Probably go with a 4x8 string where each cylinder is a node of 4 chips. 400MHz expected 700GH at about 350W (plus fans and extra crap). We're thinking what extra crap to add now, gauges and lights and stuff. Not as a priority of course, TypeZero and whatnot would still be the focus. But a lot of the design of this thing would derive directly from TypeZero specs so, you know.
So we're gonna proceed with making something look like a big V8. I'm working on an idea for a supercharger with internal fans as the air intake for the topside heatsink. Probably go with a 4x8 string where each cylinder is a node of 4 chips. 400MHz expected 700GH at about 350W (plus fans and extra crap). We're thinking what extra crap to add now, gauges and lights and stuff. Not as a priority of course, TypeZero and whatnot would still be the focus. But a lot of the design of this thing would derive directly from TypeZero specs so, you know.
that would look cool sitting on a desk.
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