Topic: [GUIDE] Innosilicon [A1 Booster + A2 Terminator] Support/Tuning - page 2. (Read 29740 times)

The MinerEU firmware has been updated and is also reporting how many cores and temperature of the cores now. please update

new miners will still have 6 module but each pcb panel will have 12 chips instead of 8 chips. which offer a total hash rate of 120M

try to connect left side of a2 chip with right side of a2 chip.

Cs_L and Cs_R and so on with the same id.

http://www.usbminers.nl/Innosilicon_A2_PG_v120140424.pdf

I've red the datasheet and left side is the master side and right side the slave side, maybe to short the two can give at the other chip the path to process hash.

Attention to do not short VDD with GND or the signal with Vdd or Gnd.

hi eraser
I have same problem with chip UA4
https://bitcointalksearch.org/topic/m.8958039

I remove it, cgminer detect blade with other seven chip, but doesn't start mine

One chip appears to be melted, maybe i can try to remove it ?
someone had the same problem ?

The screenshot you posted states 12 asic chips per board.
The device specs you copied from Zoomhash are weird: "A Total of 2 boards with 10 chip on each board, Total 16 Chips in a miner" (2 times 10 is 20 and not 16 :S )

I will change the maximum number of asic chips accepted and I will post the image.
One question: Is the turbo mode a hardware or software option?

thanks for the info.
It probably says 12 chips because it is an adapted version form the A1, which has 12 chips.
I you click on the 'stats' page you should see the temperature per chip. Could you post a photo from that? (I need the number of cores per chip and the amount of chips)
And at what frequency are you running it?
When you have indeed 10 chips per board you should be able to go to 40MH/s

Chip Specs
• Developed on 28nm using very low power design techniques and best efficiency.
• Custom IC package with power bars for low voltage, high current feeding.
• Configurable in daisy chain mode for distributed work with up to 253 ASICs.
• Standard SPI interface with CS pin needed to enclose all useful SDI and SDO data.
• 27 highly optimized hashing engines based on custom ASIC cells up to 1.6M.
• Built-in redundancy architecture to allow for bad engines to be bypassed without affecting mining operation.
• Flexibility to configure the PLL clock and computation performance.
• Hashing power of 1.6M in nominal and 1.8M in Turbo mode.
• Power usage of 10W in typical nominal and 12W in typical Turbo mode.
• Supply voltage of 0.78V in low power, 0.84 V in Turbo mode for ICs.
• No need for special cooling, just regular top and bottom heat sinks plus fan cooling.

The Device Specs
• A Total of 2 boards with 10 chip on each board, Total 16 Chips in a miner
• Turbo Mode Hash rate 1.8Mhs*20 Chips = 35Mhs +/- 8%
• Power = 350Watts normal
• Size = 51cm—42cm—16cm
• Temperature = Runs cooler than the A1 miners

[2014-09-16 22:51:32] Started cgminer 3.9.0
 [2014-09-16 22:51:32] Run Reset=1
 [2014-09-16 22:51:32] ST MCU hardware reset start
 [2014-09-16 22:51:36] SPI Speed 4000 kHz
 [2014-09-16 22:51:36] ST MCU - Enable (Pre-header)
 [2014-09-16 22:51:36] A1 = 1000,6
 [2014-09-16 22:51:36] A1 PLL Clock = 1000MHz
 [2014-09-16 22:51:36] GPIO CS is ON at CS5
 [2014-09-16 22:51:37] spidev0.0(cs5): Found 8 A1 chips
 [2014-09-16 22:51:37] Found chip 1 with 54 active cores
 [2014-09-16 22:51:37] Found chip 2 with 54 active cores
 [2014-09-16 22:51:37] Found chip 3 with 52 active cores
 [2014-09-16 22:51:37] Found chip 4 with 53 active cores
 [2014-09-16 22:51:37] Found chip 5 with 53 active cores
 [2014-09-16 22:51:37] Found chip 6 with 54 active cores
 [2014-09-16 22:51:37] Found chip 7 with 54 active cores
 [2014-09-16 22:51:37] Found chip 8 with 0 active cores
 [2014-09-16 22:51:37] Found 8 chips with total 374 active cores
 [2014-09-16 22:51:37] A1 boards=1, active cores=374, Efficient=86%, speed=10.7M
 [2014-09-16 22:51:37] Probing for an alive pool
 [2014-09-16 22:51:37] Pool 0 difficulty changed to 1024
 [2014-09-16 22:51:37] Network diff set to 33K
 [2014-09-16 22:51:38] Failed to read num_cores from chip(cs5) 5
 [2014-09-16 22:51:38] Failed to read num_cores from chip(cs5) 5
 [2014-09-16 22:51:38] Failed to read num_cores from chip(cs5) 5
 [2014-09-16 22:51:39] Failed to read num_cores from chip(cs5) 5
 [2014-09-16 22:51:39] Failed to read num_cores from chip(cs5) 5
 [2014-09-16 22:51:39] Failed to read num_cores from chip(cs5) 5
 [2014-09-16 22:51:39] Failed to read num_cores from chip(cs5) 5
 [2014-09-16 22:51:39] Failed to read num_cores from chip(cs5) 5
 [2014-09-16 22:51:40] Shutdown signal received.

Glad to see you found the problem. I have a question. I made an image that allows for more over-clocking options. However, in the code, the number of A2 chips is hard-coded. How many chips, with how many cores on each chip, does the new A2Mini have. I might be able to convert this version to fit the new A2Mini (I can't test is myself though).

Thnx