Topic: Klondike - 16 chip ASIC Open Source Board - Preliminary - page 104. (Read 435369 times)
I don't know if avalon released their firmware or not but this isn't the avalon reference design, I do know that. I'm sure it's based on it to some extent, but it definitely isn't a clone... so I doubt their firmware could just be dropped in without some changes, the extent of which is anyone's guess
So if Terrahash is starting to take orders tomorrow and you are no where near functional firmware and they expect chips in a less than a month, will they be able to deliver a functional product?
Probably. Maybe. It should not take long to get the firmware functional now. But things can go wrong and if they do then it could take much longer. If the reports from burnin of the ASIC being very fussy about it's data clocking are accurate then there is a good chance that getting ASIC comm could take us off track. Any change that forces redesign will mean new boards and at least a 2 week set back. But we don't know that yet. I'll be testing ASIC comm. initially on a K1 as it's much simpler and so I can focus on just a single chip. One of the design faults of the ASIC as far as I can tell is that it doesn't provide a way to confirm data receipt (unless that is what one of the debug signals is for - but they are undocumented, and everything else is very minimally documented.) So the only way I know of now is to feed data that should immediately or soon after give a result and check for result data output. There could have been much smarter communication design but for whatever reasons we don't have that luxury here.Well, there goes my comfort level.
Did Avalong release their own firmware? Would it help or is this design completely different?
So if Terrahash is starting to take orders tomorrow and you are no where near functional firmware and they expect chips in a less than a month, will they be able to deliver a functional product?
Probably. Maybe. It should not take long to get the firmware functional now. But things can go wrong and if they do then it could take much longer. If the reports from burnin of the ASIC being very fussy about it's data clocking are accurate then there is a good chance that getting ASIC comm could take us off track. Any change that forces redesign will mean new boards and at least a 2 week set back. But we don't know that yet. I'll be testing ASIC comm. initially on a K1 as it's much simpler and so I can focus on just a single chip. One of the design faults of the ASIC as far as I can tell is that it doesn't provide a way to confirm data receipt (unless that is what one of the debug signals is for - but they are undocumented, and everything else is very minimally documented.) So the only way I know of now is to feed data that should immediately or soon after give a result and check for result data output. There could have been much smarter communication design but for whatever reasons we don't have that luxury here. Hi Bkk,
I´m looking at Nano sch and I guess that L1 must be tied to pin 3 (SW) instead of pin1 (BST) according to the AP6502A datasheet. Please confirm that.
Best regards!
Yes. That's a schematic transcription error. Fortunately I checked the board and a small cut and solder bridge can fix it for now. Thank you for double checking - please do so on the K16 if you get some time. I´m looking at Nano sch and I guess that L1 must be tied to pin 3 (SW) instead of pin1 (BST) according to the AP6502A datasheet. Please confirm that.
Best regards!
(I haven't gotten caught up ITT)
I'm getting at least 1 sample chip (maybe a second) from one of my group buys. I'll be having a local PCB assembly house build up a K16 with one of the asics on it (one chip per pcb) and then doing some burnin and Overclocking tests, as well as thermal analysis, and then publish the results here.
Not sure when the chips will be in, but i also have the microcontrollers due to arrive at the end of june so it would be after that.
I'll have to check/talk with people about the k16 PCB assembly revision, i can build up one without asics (test it with a fixed resistive load or similar) and if it looks good, build the assembly with the asic. Especially if i have only one, i'll have to make sure it's good to go.
I think BkkCoins will be getting quite a few chips from people though?
I'm getting at least 1 sample chip (maybe a second) from one of my group buys. I'll be having a local PCB assembly house build up a K16 with one of the asics on it (one chip per pcb) and then doing some burnin and Overclocking tests, as well as thermal analysis, and then publish the results here.
Not sure when the chips will be in, but i also have the microcontrollers due to arrive at the end of june so it would be after that.
I'll have to check/talk with people about the k16 PCB assembly revision, i can build up one without asics (test it with a fixed resistive load or similar) and if it looks good, build the assembly with the asic. Especially if i have only one, i'll have to make sure it's good to go.
I think BkkCoins will be getting quite a few chips from people though?
EDIT: one is AP6502 and one is AP6502A
Your 5V*500mA calculation is based on the quiescent load I assume. So when there's no load the converter would use 2.5W.
Potentially the AP6502A would deliver 90%*2A*5V (assuming the Efficiency graph with Vout =3.3V is similar to the 1.2Vout) = 9W
Good point! I don´t get the 75%.
I guess that 5V*500mA is th USB port current limit; so 5V*500mA*0.9= 2.25W can be delivered by the converter at max current of USB port.
Ah yes, 500mA is the official limit of the USB 2.0 specification, from a supplying port perspective. However, it is very doable to get a powered USB hub providing a lot more. This is described in the 'Battery Charging Specification' (v1.2) which provides extra current for charging of devices up to 1.5A (while still being able to have a USB 2.0 comms interface).
Since the AP6502A is only needed on the K1, theoretically the converter could handle [email protected] which should be more than enough to handle the actual load estimated at <3W (equal to 3W/0.9/5V=0.67A@5V) . Many new motherboards could handle that current, not on all ports at the same time however...
EDIT: one is AP6502 and one is AP6502A
Your 5V*500mA calculation is based on the quiescent load I assume. So when there's no load the converter would use 2.5W.
Potentially the AP6502A would deliver 90%*2A*5V (assuming the Efficiency graph with Vout =3.3V is similar to the 1.2Vout) = 9W
Good point! I don´t get the 75%.
I guess that 5V*500mA is th USB port current limit; so 5V*500mA*0.9= 2.25W can be delivered by the converter at max current of USB port.
I´m looking at Nano sch and I guess that L1 must be tied to pin 3 (SW) instead of pin1 (BST) according to the AP6502A datasheet. Please confirm that.
http://www.digchip.com/datasheets/parts/datasheet/129/AP6502-pdf.php
L should connect to pin 3 (SW) and C between pin 1 and 3. Have not checked nano schemas yet.
AP6502 have only 75% efficiency 5v in 1.2v out 2A range. 5v*500mA=2.5W *75%=1.875w to chip (max. other components need power too). I recommend change better converter.
Interesting, the sheet you provide is a bit different from the one in the documentation of the klondike. The klondike sheet however is a more recent version, the date of the the sheet is December 2012 (November 2011 for sheet above). The specs show a discrepancy;
| AP6502 | AP6502A |
| November 2011 | December 2012 |
| Doc rev 2-2 | Doc rev 3-2 |
| Freq 340khz | Freq 240khz |
| Efficiency 5V@2A: ~75% | Efficiency 5V@2A: ~90% |
EDIT: one is AP6502 and one is AP6502A
Your 5V*500mA calculation is based on the quiescent load I assume. So when there's no load the converter would use 2.5W.
Potentially the AP6502A would deliver 90%*2A*5V (assuming the Efficiency graph with Vout =3.3V is similar to the 1.2Vout) = 9W
I´m looking at Nano sch and I guess that L1 must be tied to pin 3 (SW) instead of pin1 (BST) according to the AP6502A datasheet. Please confirm that.
http://www.digchip.com/datasheets/parts/datasheet/129/AP6502-pdf.php
L should connect to pin 3 (SW) and C between pin 1 and 3. Have not checked nano schemas yet.
AP6502 have only 75% efficiency 5v in 1.2v out 2A range. 5v*500mA=2.5W *75%=1.875w to chip (max. other components need power too). I recommend change better converter.
Guys and gals arguing above - could you please start your own topic and stop polluting this one?
So if Terrahash is starting to take orders tomorrow and you are no where near functional firmware and they expect chips in a less than a month, will they be able to deliver a functional product?
Cuz of course nothing can happen on this "open source" project without Bkk's sole approval, all hail BKK!
What are you implying here anyway? I've been lurking on this thread since the beginning. IMO this is clearly BKKCoins' project.
Yes, the original plans are open source, but he's made significant changes to the design. And yes, he's has help and support from a number of sources.
But the project is still "His". Every open source project has an "owner", why would this one be different? With this project, that person is unquestionably BKKCoins.
Terrahash posted "at the last minute" that they needed more details about the design, as they would be selling boards.
BkkCoins made what I feel must have been a difficult choice to release further information on a design he has yet to test. But he decided to do so for the benefit of all. I applaud him for that.
So yes, please do give respect where it's due!
So if Terrahash is starting to take orders tomorrow and you are no where near functional firmware and they expect chips in a less than a month, will they be able to deliver a functional product?
I'm answering this question with some information already posted instead of harassment.
If TH is helping the project with Firmware and Driver development, doesn't that already answer the question?
This need to quote old posts out of context as proof of someone's malfeasance is getting old. An comes off as putting words in BKK's mouth. Stop the manipulation and paranoia. As far as I am concerned TH is an asset to the project, and as only one hoop let to jump through regarding proof of chip order.
That's not the question, the question was if TH will be able to deliver in time even with the BKKCoins firmware current development stage. The answer is they can if they could fill the holes in the current development and BKKCoins is asking for debugging info and disclosure about the firmware if you're going proprietary.
I'm not creating anything, if anyone is going that way is you.
The PCB has the OSHW logo right in the middle. Therefore, the project should abide by OSHW principles stated here:
http://freedomdefined.org/OSHW
Note: I am not implying that the project is not complying with OSHW principles.
http://freedomdefined.org/OSHW
Note: I am not implying that the project is not complying with OSHW principles.
So if Terrahash is starting to take orders tomorrow and you are no where near functional firmware and they expect chips in a less than a month, will they be able to deliver a functional product?
I'm answering this question with some information already posted instead of harassment.
If TH is helping the project with Firmware and Driver development, doesn't that already answer the question?
This need to quote old posts out of context as proof of someone's malfeasance is getting old. An comes off as putting words in BKK's mouth. Stop the manipulation and paranoia. As far as I am concerned TH is an asset to the project, and as only one hoop let to jump through regarding proof of chip order.
So if Terrahash is starting to take orders tomorrow and you are no where near functional firmware and they expect chips in a less than a month, will they be able to deliver a functional product?
I'm answering this question with some information already posted instead of harassment.
BkkCoins,
We have received Avalon sample chips. We did get about 10 K16 boards manufactured locally as well. We want to assemble one board to help with development and testing. We have resources here that can help push the project forward.
Can you upload the silk screen for the components (those nice little labels that indicate which component is to be placed where on the board)? And if possible XY data that can be fed to an SMT machine?
Wow. This is news to me. And frankly it terrifies me that so much has been invested in my design when I haven't even been able to verify it. However, I'm not going to stand in the way despite the feeling that control is being wrestled away. We have received Avalon sample chips. We did get about 10 K16 boards manufactured locally as well. We want to assemble one board to help with development and testing. We have resources here that can help push the project forward.
Can you upload the silk screen for the components (those nice little labels that indicate which component is to be placed where on the board)? And if possible XY data that can be fed to an SMT machine?
I'm ready to release everything I have along with a proper open source license but first I would need two things - 1. A public commitment that any info derived from testing/debugging will be submitted back quickly so that everyone has access in a timely fashion. 2. A disclosure regarding any independent firmware and driver development and whether you plan to use proprietary code to enter the market first.
The lack of past communication makes me concerned that your main goal is to gaining competitive advantage, and that my materials will be used towards shutting everyone else committed to assembling units, and who have been communicating with me daily, out of the market.
Foul! out of context! keep reading........
BkkCoins,
We have received Avalon sample chips. We did get about 10 K16 boards manufactured locally as well. We want to assemble one board to help with development and testing. We have resources here that can help push the project forward.
Can you upload the silk screen for the components (those nice little labels that indicate which component is to be placed where on the board)? And if possible XY data that can be fed to an SMT machine?
Wow. This is news to me. And frankly it terrifies me that so much has been invested in my design when I haven't even been able to verify it. However, I'm not going to stand in the way despite the feeling that control is being wrestled away. We have received Avalon sample chips. We did get about 10 K16 boards manufactured locally as well. We want to assemble one board to help with development and testing. We have resources here that can help push the project forward.
Can you upload the silk screen for the components (those nice little labels that indicate which component is to be placed where on the board)? And if possible XY data that can be fed to an SMT machine?
I'm ready to release everything I have along with a proper open source license but first I would need two things - 1. A public commitment that any info derived from testing/debugging will be submitted back quickly so that everyone has access in a timely fashion. 2. A disclosure regarding any independent firmware and driver development and whether you plan to use proprietary code to enter the market first.
The lack of past communication makes me concerned that your main goal is to gaining competitive advantage, and that my materials will be used towards shutting everyone else committed to assembling units, and who have been communicating with me daily, out of the market.
So if Terrahash is starting to take orders tomorrow and you are no where near functional firmware and they expect chips in a less than a month, will they be able to deliver a functional product?
Cuz of course nothing can happen on this "open source" project without Bkk's sole approval, all hail BKK!
Looking at the pdf`s and terra`s photo of populated board https://bitcointalksearch.org/topic/off-topic-198489
Is probably enough to get me going so dont waste too much time on it..
Thanks for the link. I hadn't seen it yet.Is probably enough to get me going so dont waste too much time on it..
I'm not sure they realise over there that this isn't going to plug in and mine right now. A lot of the code is present but it's not debugged and it will require quite a bit of work still to get it working as expected, not to mention there is no driver yet for cgminer. So the best case initially is using the ktest program to feed test data and getting any result nonces back.
I've been working today on a kslog utility which takes sharelog data from cgminer and decodes the merkle and midstate data so that suitable test data that is known to give a nonce result can be fed in with ktest. Also, this data is used for the chip detection algorithm so it's needed for completing the firmware. kslog is written and works but I have no idea if I got the endian swaps right. It outputs python and C syntax data statements to use in ktest and the firmware.
So if Terrahash is starting to take orders tomorrow and you are no where near functional firmware and they expect chips in a less than a month, will they be able to deliver a functional product?
That being said, it's very easy to put the Avalon chips on the board by hand (using an iron or a hot-air rework gun). I could attach 16 QFN chips in less than 16 minutes.
Enigma
Enigma
Unless you're working with an oven, that's a complete bullshit..
I'm not talking about in an oven - I'm talking about using a hot-air rework gun. If it took one of our rework techs more than two minutes to replace a QFN48, they'd be fired.
Enigma
Enigma
Please, stay on track with the thread.
Enigma
I know, that's why I'm asking you to stay on track.
By the way, you're talking with people who knows what they're doing too.
and please answer this first.
Please do tell us how you'd solder 1 QFN/minute.
http://store.curiousinventor.com/guides/Surface_Mount_Soldering/QFN
http://store.curiousinventor.com/guides/Surface_Mount_Soldering/QFN
I'm done, have a nice day.
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