1. Chip specifications
There are substantial differences in the way the BFL chip is produced. They do employ a standard cell ASIC, while we went for a custom design with a focus on performances, achieved via a complex place & route procedure, which took our team almost one full-immersion month of work to complete.
We do confirm that we're expecting to obtain the initially declared performances with the 130nm round, but we will wait for the ICs to be ready, to better assess the yield quality in terms of chip grades.
2. 130 nm vs. newer technology
While 28nm technology is indeed superior, if fully taken advantage of, the NRE costs are enormously different, and so are the skills needed to design a working chip. We don't have the required resources, and we do not think the results obtainable are worth the costs right now, this is a strategy we will explore in the future.
We are happy with the obtained high performances and low consumptions with 130nm and we will show another breaktru' when the 65nm design is ready.
3. ETA
130nm IC is estimated to be delivered in early September and to be mining 7-10 days later.
65nm IC is still under development and no ETA is available yet.
4. General timeline
The following days we will focus on Q/A session and on the normal activities pertaining to our project.
As per your request of more pictures, here are some images of our test environment, with the WR703N router working as real world interface for the simulated IC running on the fpga.
Please provide
detailed chip specs. Remember you are stating that you are able to get chips working at
4.8GH/s on a 130nm node (that's the equivalent of
~17 Avalon chips, which are built on a smaller die size of 110nm), using minimal power. What is the process?
Die size? Voltages? Frequency? Etc?
I'm sure you already have most of these specs set in stone since you are aiming for an early September delivery. Has the order been done with TSMC already?
Please also show a pic/video of the prototype FPGA hashing at 4.8GH/s.
Example of
detailed chip specs:
Avalon chip
Technology Summary:
TSMC 0.11- micron G process
5 Metal
Core Voltage: 1.2 V
I/O Voltage: 3.3 V
Core Frequency: 256+ MHz
Number of Pads: 48
8 Data
40+1 Power
Package Type: QFN48 -0.5 Pitch
Packaged Chip Size: 7 mm x 7 mm
Chip Interface
Data Pins (8 in total):
Clock i
Serial Data In [2] i
Serial Data Out [2] o
Serial Data Bypass [2] o
Reserved [1] -
Chip power efficienty: 6.6W/GHs @ 1.15 V
