If those are the correct specs, then I'm sorry but... LOL!!!
For that to be possible, not only each Labcoin core would have to be
~42% smaller [65/130*(6.5^2)/(7.1^2)] than each BFL core but also the Labcoin chip would magically operate at a
higher frequency (300MHz vs 250MHz) while keeping the same power draw...
Since there are several new companies going for the 130nm route with the excuse that manufacturing costs are much cheaper, might as well burst that bubble too:
It's not. Nothing beats going 28nm
now, except for the fact that the upfront NRE cost is much higher.
ACTM wait up to six months. . LOL. . . Time is money
It is of course up to all investors to draw their own conclusions and believe what they want regarding what density (130, 110, 65, 55 or 28 nm) deliver the best ROI over time.
labcoin has made the choice to go with 130 nm as gen 1 and 65 nm as gen 2 for several reasons. Some of these reasons are NRE costs, fabrication costs, available developer resources, capital procurement and availability of Foundry shuttles and production slots.
We are certainly not claiming that 28 nm is a "bad choice" by default, but for a smaller project not wanting to be forced to raise millions of dollars and bet "everything" on a single development project or risk total failure (Bitfury did this, and it seems they were lucky enough to actually come out with positive results). Then staying with lesser density that is cheaper and offer far more flexible production options just makes sense.
Maybe worth pointing out that the graph you pasted has almost no relation to ANY ASIC manufacturer as it refers to large scale generalized production of IC. As as much as I would like to think that Labcoin shortly will be ordering $100 million dollar IC production runs I doubt that is very closely connected with reality.
The only real difference is NRE cost and having the expertise to develop on 28nm, that's the real bet.
Bitfury went full-custom standard cell and it worked OK for them, but that's the risk of going full-custom at first. You have the same risk, since your 130nm chip has a lot of sketchy specs. I would rather you commented on those, especially on the part where you claim to develop a faster and more power efficient chip than BFL (also standard cell) with transistors that have DOUBLE the size (130nm vs 65nm) and require much higher voltages (
power consumption scales with the square of voltage).
The graph above is for
ANY ASIC manufacturer, as it compares a
Normalized Transistor Cost (wafer cost + packaging + etc) to a
timeline, based on
yields/wafer,
die sizes and
wafer cost. The production costs on new die sizes quickly go down after some time.
