Topic: Modular FPGA Miner Hardware Design Development - page 12. (Read 119276 times)

I don't know how much memory the final design will need, but at the start if we want to just use the MSP430 as a glorified USB to Jtag adapter the current part should be fine, if we wanna say load the bitstream and everything from the uC, I don't think it'll be a good idea, we should just leave that for the motherboard design stage.

Basically I don't see a need to move to a bigger/more powerful MSP.

Anyway, the important thing is that we move from the 5504 to a 552x, so the schematic will need to change.

Well, limiting the amount of flash memory could end up being a pain, and the difference in price between the 5524 and 5528 is something like 10% more, I think the added flexibility is well worth it. Who knows what kind of functionality might be added to these boards in the future!

These come preprogrammed with the USB bootloader. We should certainly break out the pins needed to reprogram it in case it is somehow overwritten. I think that to enable the bootloader, you need to pull the /RST pin low, so we need to connect that to a button or a jumper. Someone please make sure I'm understanding that correctly, don't take my word for it!

8 ADCs should be plenty. What's more interesting is the number of USARTs (at least 2, 3/4 would be optimal). I'd also think that 64kiB of flash should be plenty, as this one really doesn't have to do anything complex, just relay data between the backplane/USB and the FPGAs.
Oh, and how can these MSPs be flashed, or how easily can they be bricked? Please provide a standard 2.54mm header (or at least the PCB pads for one) for the pins needed for reprogramming.
Is there a readily-made USB bootloader for them that could be enabled either via USB itself or via a jumper? How big is that one?

I finally had time to do some reading about the differences between all of the MSP430F5xx's. To summarize, the primary differences is the size of the flash memory and the SRAM. The amount of memory needed should to be estimated by someone who will write the code (most likely not me, I've never programmed an MSP430 before). If we don't have an estimate, we should err on the side of more memory, because it probably doesn't influence the price all that much.

The other differences basically boil down to the number of ADCs and IOs. ADCs will be useful for monitoring temps and voltages.

The 5504 has only 8 kB flash memory and 4 kB ram, most likely not enough. If you move up to the 5507, we change nothing except increase the flash memory to 32 kB. There are 8 ADCs and 31 total IOs on these.

If we need more memory or IOs, the next up is really the 5524. This one has 64/4 kB (flash/ram), 10 ADCs and 47 IOs.

The top of the line is really the 5528. This one has 128/8 kB, 10 ADCs, 47 IOs. This one would definitely work for us, even if it was a little bit overkill. 

Just looked at the prices and it seems like the 550x series is all out of stock, but is around $5. The 552x series is available, and is more like $10. The extra $5 is negligible on this board, and gives us much more wiggle room, I think.

O_Shovah, I unfortunately don't have Eagle available so I can't look at your schematic. Can you make a PDF or image of it?

I'm taking the plunge and getting the ZTEX LX150 board to teach myself about FPGAs, and provide feedback on the real-life performance of the LX150.

I'm a software developer and electronics hobbyist at heart, but FPGAs are a different animal completely so support by the experienced people here will be much appreciated   

Changed the daughterboard block diagram on dropbox a bit:

• Added a separate power supply for the MSP (delete again if we decide to just reset the FPGAs instead)
• Explicitly wrote SPI instead of data for the bus

Maybe just to prevent one of you to overwrite te work of the other .

I created two folders for each of you respectivly so you may save your variant in you folder.

I also propose we  add date and time to the file name so we may backtrack them a bit.

No specific reason why I went in from the other side, for the termination resistors. I've done up the PSUs for both Vccints, feel free to move them around if there is a need to.

We need to roughly combine the work together, else there's no way to put in the rest of the parts, i.e I need to ripup alot of your work to get stuff to fit in.

I've also reworked the PSU and the FPGAs to bond their GNDs to the 2nd layer pls check the layout. Vccio is mostly routed except for the SMPS module itself.

@li_gangyi: I looked at your FPGA_pin_combined.brd. and I have a few questions:

• When you changed the routing for the termination resistors, is there a specific reason why you went in from the other side? Both seemed equally good from my point of view, so I am confused.
• Do you think the individual schematics and board layouts are at a level that merging them makes sense? I thought there is quite a bit to do for my board at least, so there are a few iterations there. And once it is merged we cannot work on the thing at the same time.
• Otherwise we have to find a way to collaborate while working on the same files. Working on different files is a first step, because then we don't undo the other persons work. If we work on the same file, maybe we can ask here when a file is "free" to work on?

I wanted to do the following to the FPGA board, maybe this evening:

• Shift GND to layer 2 and VCCINT to layer 15 as suggested by pusle, li_gangyi and fizzisist and shift VCCIO and routing to layer 4.
• Look at the bus routing to move the wires further apart

Personally it doesn't look too bad to me, I just need to check that we are meeting requirements for decoupling capacitors.

GND on layer 2 would be best, however we'd have to put in blind vias to link up the top to 2nd in order to still make the rest of the space usable. I might have gone overboard when testing it out though, I had vias going from almost every node to the 2nd layer.

I'll add in the PSUs to the new board layout later.

Edit: Ok added it in, we're gonna have to touchup the IO routing abit, let me finish up the rest in the next few hrs.

Sounds like somebody read the document I sent   

I uploaded your files to Dropbox (I don't use the web interface). I don't have Eagle on this computer, so I wasn't able to look closely at your changes.

To your other question about layer stackup, part of the reason to put GND and VCCINT on inner layers close to eachother is that it increases the capacitance between the two, thus helping with decoupling. Having them as complete planes helps reduce the size of current loops, because the return path for a signal (for example) will always run directly below the trace on the outer layer above it. At least that's my understanding.

How does layer GND=layer 2 and VCCINT=layer 15 (so vias for both signals) compare to GND=layer 1 and VCCINT=layer 16 (so only vias in one signal)? If you want to minimize inductance, then this should be even better. And having GND on layer 1 means that there is no ground below every pad, so less capacitance as well. Or does one want to have lots of that?

It should now be much easier to change GND to layer 2, since VCCAUX is gone. But then we have MANY more vias! Current via count is 261 vias, price break is at 300.

To things form my side.

@ pulse: If the email adress shown in the forum is valid you should be invited to the dropboxfolder by now.


Regarding my MSP schematic: It seems i missed something on the usb connection side on wich somebody may please have a look.

In addition there is an additional clk in and output (Xin and Xout). Im not shure if this is nessecary or may also be driven internally by the Aclk source. Please also somebody check on that.


I am also currently experiencing problem for uploading
i hope they fix it soon.    

Hey guys,

In case you haven't seen anything about it yet, you might want to read this:

http://forum.bitcoin.org/index.php?topic=29696.msg383806#msg383806

I see TheSeven has talked to this guy in the past on the boards, but I just thought it may be interesting for you all to look at.

Carry on, and keep up the good work!

I uploaded a new version of the schematic, board and PDF+PNG to github. Couldn't upload to dropbox for some weird reason (upgrade to newest Flash?, worked yesterday).

Changes:

• VCCINT is now split into two signals VCCINT0 and VCCINT1 for the two different FPGAs
• VCCAUX is gone, merged with VCCIO
• Layer 2 contains no polygon anymore
• The different FPGAs are spaced further apart, polygons no longer touching
• The termination resistors are folded to the back, reducing the size by half

TODO:

• Unfold the bus to not have several signals on top of each other
• Merge with PSU (again) and MCU

I did this before pusle posted his more detailed explanation. Can you actually look at the file from github and say how bad you think this is?

Also: can someone copy the files to dropbox, because I cannot.

pusle, thanks for your comments. I agree with everything you said, including about the Xilinx licensing. If you're a student, you can likely get a free license because they know it will likely mean more chips sold in the future.

Please send a PM to O_Shovah to get access to our shared Dropbox folder.

About the ISE issue...

I have some contact with Xilinx through work and their business model is selling chips, not software.
As long as it doesn't cost them anything in support/FAE they could not care less where you got your ISE from.

version 13.1 is "out" btw.



About the pcb board layout:

Noise coming  from the feedback pin is a non issue as it's very high impedance compared to the main rail.
The ripple from the switcher and the noise from the FPGA are all already on the VCCINT and dwarfing any other contribution.

When you draw 5 amps you'll be surprised how easily you get lots of mV droop and the FPGA needs
tight tolerance for the core supply. Feedback from near/under the fpga is the best way.

But you should put the divider resistors close to the switching power as li_gangyi  mentioned.


Layer 2 for gnd is because it gives the least inductance for the GND via's.
Same reason for using layer 3 for VCCINT.
Layer choices isn't that critical, but having proper power planes, especially for Gnd IS important.
Sure lots of times the most crazy routing works, but it's best to do what you can to not end up
with a board that behaves in "mysterious ways" 

Could you please give me a link so I can  have a look at the pcb file?

Remember: if all the modules on the motherboard are shut-down (but drawing ~2W each), it is possible for the motherboard logic to turn off the ATX power supply. That is that only logic that needs to run off of 5V. Sorry for the confusion.