Topic: Modular FPGA Miner Hardware Design Development - page 15. (Read 119276 times)

For mining you need three things: you need to be able to load a bitstream into the FPGA, you need a clock and you need to communicate with the firmware inside the FPGA afterwards. A slow communication link (>1kbit/s) would even do, but more is (slightly) better. That is all: no extra pins needed. For debugging, an extra LED or a few pins may be useful, but as you have to have a working connection to talk to the thing, it is not critical in my point of view (I will bow to the greater experience of others, though).

Routing all IOs out is a complete waste of money if you are building a mining board. If you do something else like building a video-transcoder, a DNA folding computer or whatnot, it may help. But for mining? If they had the FPGA in a 50-pin housing, it would be plenty!


No memory needed. The basic algorithm has been designed to not need a lot of memory. Look at the code others have announced in this forum thread. It already works well, even if there is no version directly for our FPGA. If you read the HDL code, you see that calculating SHA-256 amounts to a lot of register pipelines, but no memory needed.

I assume it is because you have not been given access to the directory. I will post the stuff somewhere else in addition to dropbox.

Edit: It has been decided I was going off on an unnecessary tangent here.

If we want the MCU to be able to turn the power supplies for the FPGAs on and off, it should be bus powered. If USB is being used, we are talking  5 volts, 500mA (100mA without permission).

If the FPGAs have a small enough 2.5V current draws, no extra part is needed. According to page 7 of the datasheet "...Spartan-6 devices do not have a required power-on sequence." (Table 6 note 2).

I couldn't really find anything saying you can power up V_ccaux and V_cco with V_ccint unpowered more explicitly.

So ok lets agree on a test board.

Just to throw some numbers in here:

Maybe 150mm x 100 mm maximum size so there's no need for space optimisation in the first place.

Barrel connector , Molex connector for power . Power supply as planned by li_gangyi

Msp 430 and mini usb port

FPGA routing as Olaf.Mandels setup but with the options to rout unused IO pins either to ground , Vaux or left floating by Jumper settings.
(other modifications essentially nessesary ?)

I would leave away the 240 Pins of the DIMM card just to keep it simple for the first time.

Pin header for the Spi BUS system normaly going to the motherboard.


Another idea would be to produce each of the subparts ( power supply , FPGa setup, Msp430 and USB) on an individual board (maybe two of the MSP430and USB boards to simulate motherboard) to make it possible to test them in their one all being connected by pinheaders and jumpercables.Aso this would only need one 4 layer and 2 two layer boards.
(this last one is just a option i dont know how much the boards signals ar affected by long connection lines)


@li_gangyi:
it seemed Bahnfire had some experience on this matter. I personally remember the fpga's internal memory to be sufficient. Maybe our FPGA programmers could also give a hint on that subject.

This would be why we need those FPGA guys right now, what kinda IOs are gonna be required? Is jtag and what not we have now sufficient? If we need more IOs that what we have planned now, I don't think a 4 layer board is gonna to suffice, if we want to route out ALL the IOs, that's gonna take at least another 2 layers IMO.

Do we need some sorta external memory for 'bitcoining'? If we later decide that we need it, it's going to require a new run of boards, there's no easy way to add the functionality later. I.E even with all the IOs routed out it's not much help. I'm willing to fork out money to produce the 1st batch of boards, but without these critical bits of info, we're shooting in the dark. We're gonna need some guy or girl for that matter who has dabbled with this, and knows for sure what we need, otherwise we'll just end up producing a dev board in the end to get to the results.

We're working on a smallish budget, let's put in solutions that are known to work, instead of stuff that 'should work', if it's new ground, we should trash it out and discuss it before putting it into the design.

I agree with bahnfire that the prototyping will be much easier if we don't try to fit it to the final dimensions, and we should include as much flexibility and debug-ability into it as possible. On the other hand, though, we should do our best to make this board useful as a mining board if we're lucky and it happens to work. For that reason, it should include all of the features of the real board, including USB and DIMM connector.

On the same line of thought, I'd be willing to put up part of the investment for a 3 or 4 board prototype run, if I could get one of the boards. I'm sure others feel the same way. In this way, we will have a sort of private beta test, where the people willing to put up the money can participate.

I also have oscilloscopes, power supplies, JTAG programmers, Xilinx license, etc., at my disposal so can help with the testing and debugging.

I am willing to invest some of my resources as needed - I have access to many supply chains and resources (my company has a factory in China and I can help purchase items from there). I also have a full test lab (oscilloscopes, testers, etc) and have contacts with many US and China PCB/SMT houses for prototype and production.

I see your point.
Im willing to invest a certain amount of money but as a student i will be limited to a few hundred Euro.
Creating a testable board sure is a good way i second that.

Does somebody disagree or as some founded other ideas? 

What I was saying RE: the extra pins was to take as many as you can and connect to individual test points not to just one. If you are working on a prototype this is the way to do it since you have easy access to pins if you need extras and will not need to do a whole new board spin (especially since this is a BGA). For production you can remove as many of these points as you can without sacrificing your future debug capability.

My opinion (and based on many years of experience): The goal should NOT be to design the first prototype(s) with the final dimensions (PCB size) as this will bit you later. You should always build a larger PCB that has all components and maybe a few extra items for testing to allow for easier debugging, dead bugging, and testing. Once the prototype is proven you can move to a smaller iteration of the PCB. Designs similar to this module could take several PCB runs from prototype to production.

If we do not do this we will run the risk of this adventure costing a lot of money and time.

I really know almost nothing about this stuff, but can OSHW help us? http://freedomdefined.org/OSHW

Olaf.Mandel, I'm logged in to Dropbox but I don't see your picture posted in the forum. I think you need to place the image in your Public folder, then copy that link. Also, as far as I know, there are only two options for shared folders with Dropbox: shared or not shared. There's no way to grant read access to everyone, etc. I think that the Dropbox is the most convenient way to easily exchange these files at this stage. Once we get some files closer to finalization, we might want to create a wiki.

About the FPGA design, why tie those pins to anything? I'll admit I'm a little confused about the HSWAPEN pin and all of this. The documentation doesn't seem to provide a clear answer, at least in my reading. In case of a mistake, bahnfire's suggestion to leave the option to change it after the fact is best. I think his idea is to connect all of the unused pins together, then leave that net unconnected to anything. If we want to connect it to GND, we can jumper it. This is best done with a small "solder jumper" part in Eagle, or a resistor part where we can load 0 ohm.

I m sorry.I m afraid this is not possible. When i grant someone access to the folder he has read, write and delete rights to all files.
I personally think a public acess would give the risk of someone not participating spoiling the content(i allready made such experinces).
I allready do a backup every evening.

There is a way to get the files to a public folder with only read access, but in that case you'd need to link every single file and syncronise them manually.

I m working on another solution at the moment. Maybe i can setup an exchange system on one of my servers.   

I get it: you don't see the picture I posted unless you are logged in to Dropbox (yes, there is a picture).

@O_Shovah: I was expecting to share the design with everyone, not only the people who contact you. Can you open read access to everyone?

I don't quite get what you meant here: each pad to a testpoint? Forget it, not in 4 layers with that trace width. All pads to one one testpoint? What is the point? And then you risk having floating inputs with no driver on the signal at all.


There are no vias for GND: it's the top layer. There is just no space for the polygon around the centre of the FPGA, so the GND traces get relatively long.

So Dropbox access means not only write access but even read access? Then how did I manage to add the picture? Or is this just security by obscurity, where you have to guess at the URL?

Agree - but this can be taken care of by using a directed pour and many vias. I will need to gain access to the dropbox to check the FPGA routing, but you normall do not want to have long traces from the FPGA balls - you would just use a slight offset and a via to the GND layer.

I would change the unused pins to either be jumpered to GND or leave open with a testpoint/pad. This way you do not design yourself into a hole/corner.

If you say so the power supply will certainly do its job.
Bahnfire offered his help a while ago regarding progamming MSP an FPGA and for the FPGa binary we may come back at TheSeven and others so this should be possible to solve.
You need the ISE suite for coding and compiling binaris for the FPGA.I remember it to be~2000$ a year so its far form being feasible for me.
They are provided both by Xilinx directly and by Avnet.



So i see we are moving towards a GPL licensing, im ok with  that. The founding a company was just a idea i would have assigned the most security but never mind.

I have just three questions left regarding this licensing type;

As far as i know the GPL doesn't restrict the use to noncommercial use. So there is the option of any company selling out idea for profit as long as the also forward the license including the original authors.

I know the GPL just for software products. Is it this unprobhlematic to directly transfere it to hardware ?

As you proposed we should start a file defining who has generated wich part of the project so we mai define copyright later.

I dont want to sound greedy here but as the copyright only covers hard- and software i would like to have a way to credit all participants like TheSeven, others and me who just participated in a advisory or organisational role.

Which guy? The one thread is here. The user is ArtForz in post #30

Pusle was the one telling me of his 150mhash/s in ISE. He said the design wasn't complete and that it should be possible to pump out much more than that. He (or someone) said that FPGAMiner was able to achieve 190mhash/s on the LX150. But I haven't really been able to find any posts from FPGAMiner stating this.

I've been cramming a lot of information RE bitcoin and FPGA for the past week. So it's all still kind of jumbled in my brain.

By my calculation

16 LX150 chips on a x1 pci-e card = 3Ghash/s
16 Chips = 2480$ (at web advertised prices, should be possible to get it for less)
PCB FAB, PSU, ETC estimated that it couldn't cost much more than 250$ per board with a large order.
So, 3Ghash/s for roughly 2730$ (probably less). About 1.09Mhash/s per $ which is more cost effective than a 6990 currently (not to mention the 300 watts of electricity you'll save per GPU you replace).

From what I understand the biggest downside of the LX150 is that it's hard to roll 1.5 engines per chip due to design issues. Again, from my calculations (which are probably wrong in some way). The LX150 could do 3 partial engines using 120K of 150K LU and generate 3hash per 2 cycles. With real world values of around 250mhash/s per chip.

I've got an EE in the family but i'm not savvy to this stuff myself. I was planning on financing the building of some FPGA boards but i'm finding it hard to get accurate figures. Hence why I need a dev board so I can just find out for myself.


Thanks for that, looks like a perfect dev board.

What do those licenses cost?

Where do I get an ISE license? From xilinx directly? Avnet?

As for dev boards, the $995 is probably the "Avnet Spartan-6 LX150T Development Kit" (http://goo.gl/S8oHN). This is a LX-150T board (note the T). The upside is that includes the ISE Logic Edition software, node locked to the LX-150T device. Normally the unlocked ISE Logic costs ~$3000

The cheapest board that I found at $750 is this:

The Opal Kelly EM6010-LX150. USB 2.0, externally powered, and with a LX-150 (no T). http://goo.gl/LbCWu

It doesn't include an ISE LE license though, so unless you already own one (I certainly don't) you won't be a happy customer.

For volume orders (50+), the price of the EM6010-LX150is $649,99. Another price reference point for us perhaps. Still way above the design target cost for the Modular FPGA Miner.

The main purpose of using the LMZ modules is so that we wouldn't have to do this, I have real life experience with these modules already, and I know they work as advertised, if anyone still wants to make a test PSU, I can ship out some LMZ modules for free to cut down on costs (this are like $15 a pop), eval kits are also available if you just wanna see how well they work.

I propose we route out the rest of the board, make a test batch of PCBs and then I can populate the board with say 1 FPGA to cut down on costs, and then ship them out to software devs who can then figure out what to do with the MCU and FPGA coding. Right now I'm not too worried about the hardware design, I can see active development, but no software dev has stepped up to offer help just yet (or maybe I'm just missing their posts). I'm no good with MSP430s just yet, so I can't help here.

Who was playing around with it? I'd like to contact that guy to avoid duplicating effort
$9000 is certainly way off, but you should also consider the cost of board production, power supply components, and higher prices if you order lower quantities. If you include the cost of design and prototyping respins, $9000 might be close for the first couple of boards. Once the design has been polished I'd think $2000 for 1.2ghash/s might be possible.