Just to backcheck this.
I am currently using the MSP430F5504 in my layouts.
Is this one suffiecient or do we want to use a 552x model ?
I that case i would have to change some parts of the routing.
Topic: Modular FPGA Miner Hardware Design Development - page 13. (Read 119276 times)
I don't remember seeing anything explicitly written about VCCINT being off, but I would guess this is actually deleting the configuration.
As long as it doesn't destroy the FPGA and doesn't draw excessive power on 2.5V, this should be fine. If we would completely power it down, it would delete its configuration as well.
But yeah, the reset 0.1W look good. Does it even make sense to shut down the PSU in this case? I'd guess that an idle dual-FPGA DIMM (just the MSP running) could be brought down to ~2W (mostly switcher quiescent current) that way, which sounds OK to me, if we can save an additional 2.5V rail that way.
I can add a LDO to power the MSP430 if you guys think the hibernation mode on the FPGA is critical, I don't think leaving the Vccaux on all the time while the device is hibernating is a good engineering practice. Only Xilinx can answer if that's a good long term strategy, because it seems like it might work, since you're holding the FPGA from turning on.
The next best thing (instead of switching off the PSUs as well), is to just put the FPGA into what's know as the "Quiescent Current Level" stage, UG394 describes more of this.
O_shovah: nice work, I'll add the MSP in later into the combined board we have now.
The next best thing (instead of switching off the PSUs as well), is to just put the FPGA into what's know as the "Quiescent Current Level" stage, UG394 describes more of this.
O_shovah: nice work, I'll add the MSP in later into the combined board we have now.
I added the USB pullup resistor and the external 25 mhz clock source to my MSP setup.
(Standby# pin of clock source is left floating to provide constant clock output)
Just uploaded it.
Please check on possible errors.
(Standby# pin of clock source is left floating to provide constant clock output)
Just uploaded it.
Please check on possible errors.
[...]
Seriously, a switcher is overkill for this. Its quiescent current will be higher than what an LDO would waste.
Being able to switch off the MSP power doesn't make any sense to me, and I'm not sure whether it's neccessary to be able to switch off the FPGAs.
Does someone have information on how much power they draw if one puts them into programming mode, or whether there's even a dedicated shutdown mode for them?
Is it allowed for the 2.5V rail to be on but the 1.2V rail to be off? If yes, how much current would the FPGA draw in that case?
Seriously, a switcher is overkill for this. Its quiescent current will be higher than what an LDO would waste.
Being able to switch off the MSP power doesn't make any sense to me, and I'm not sure whether it's neccessary to be able to switch off the FPGAs.
Does someone have information on how much power they draw if one puts them into programming mode, or whether there's even a dedicated shutdown mode for them?
Is it allowed for the 2.5V rail to be on but the 1.2V rail to be off? If yes, how much current would the FPGA draw in that case?
Why switch off the MSP? That makes no sense to me, too. The FPGA has several stages of power saving (a little bit explained in UG394):
| Name | Power consumption |
| Normal operation | ?? 7,6W ?? |
| Suspend | ?? 4.5W / 0.06W |
| Reset | 0.1W |
| Off | 0W |
In the above table, I am especially unhappy about the Suspend mode power consumption: All I can find is a reduction of current by 40%, but is that from normal operational levels or from reset levels?
I don't remember seeing anything explicitly written about VCCINT being off, but I would guess this is actually deleting the configuration.
[...]
I also agree the MSP should be powered by the power solution of the fpga.The level shifters would add adtitional parts and complicate things so we my use this in another version.
[...]
I also agree the MSP should be powered by the power solution of the fpga.The level shifters would add adtitional parts and complicate things so we my use this in another version.
[...]
Careful: you are killing one of the original features here: if the MSP is not powered from the USB connector, then it cannot enable or disable the power for the FPGAs. This was (at least for me) an important feature. And I don't see the problem, actually: you just need an additional small switcher that hangs on the USB power pin and outputs 2.5V. No reason to talk about level shifters or anything.
So you just call for an additional littel 2.5 V source just for the MCU in order to make it independent from the FPGA power supply? If thats teh case you are cerrtainly right. I thought you wanted to use an centrall power supply controler in addition.
Sorry for the misunderstanding.
Seriously, a switcher is overkill for this. Its quiescent current will be higher than what an LDO would waste.
Being able to switch off the MSP power doesn't make any sense to me, and I'm not sure whether it's neccessary to be able to switch off the FPGAs.
Does someone have information on how much power they draw if one puts them into programming mode, or whether there's even a dedicated shutdown mode for them?
Is it allowed for the 2.5V rail to be on but the 1.2V rail to be off? If yes, how much current would the FPGA draw in that case?
I would, too, if there wasn't the issue with the software: where to get the ISE Logic edition for a reasonable price (<<1kEUR)?
Yeah, that's the main issue here. There's always the 30-day trial to start with. I was actually going to write Xilinx and see if they are willing to contribute some ISE licenses to this project, provided that it is properly open sourced. I wouldn't write them however until we have a clearly stated project license type in the first post, or a webpage. Xilinx seems to support educational and non-commercial institutions, I was able to find some references to Xilinx license donations.
[...]
I would [buy a board], too, if there wasn't the issue with the software: where to get the ISE Logic edition for a reasonable price (<<1kEUR)?
I would [buy a board], too, if there wasn't the issue with the software: where to get the ISE Logic edition for a reasonable price (<<1kEUR)?
Isn't this still a problem for our design? I thought we will have to rely on people like me who have an ISE license.
It is, but if I don't have the software, I concentrate on the hardware. If I had the software, I might dabble a bit in both.
[...]
I might get the board just to get a start with FPGA's, but otherwise it is reassuring that we seem to be on the right track complexity and price-wise.
I might get the board just to get a start with FPGA's, but otherwise it is reassuring that we seem to be on the right track complexity and price-wise.
I would, too, if there wasn't the issue with the software: where to get the ISE Logic edition for a reasonable price (<<1kEUR)?
Isn't this still a problem for our design? I thought we will have to rely on people like me who have an ISE license.
where to get the ISE Logic edition for a reasonable price (<<1kEUR)?
I've been wondering about their pricing model. One guy in a previous post on this thread was saying there is a yearly fee associated with the software? I've been looking online and haven't been able to verify that claim. There are used versions of the Design Suite (12.1 and 12.3) on ebay for few hundred to 1K.
[...]
I might get the board just to get a start with FPGA's, but otherwise it is reassuring that we seem to be on the right track complexity and price-wise.
I might get the board just to get a start with FPGA's, but otherwise it is reassuring that we seem to be on the right track complexity and price-wise.
I would, too, if there wasn't the issue with the software: where to get the ISE Logic edition for a reasonable price (<<1kEUR)?
I don't know about the others, but I am in it for the fun of developing a board. The board you linked may be a very good start to get FPGA developers to write code, but once our board is go, it won't be cost effective (unless you figure their support and warranty are worth the price). I am not arguing against the board: it is good for early adopters, but eventually we should beat it.
I agree 100%, that's exactly why I posted this, perhaps not being too clear about it. I treat this as a reference point, perhaps to learn from the design also.
I might get the board just to get a start with FPGA's, but otherwise it is reassuring that we seem to be on the right track complexity and price-wise.
I have just put a schematic of my current use of the MSP IO pins into the layout folder.
Its using the naming you have used on your fpga.
Its certainly not complete but a startup.
Its using the naming you have used on your fpga.
Its certainly not complete but a startup.
Did cosmetic changes to the design: Vccio should point upwards.
I have just put a schematic of my current use of the MSP IO pins into the layout folder.
Its using the naming you have used on your fpga.
Its certainly not complete but a startup.
Its using the naming you have used on your fpga.
Its certainly not complete but a startup.
[...]
The ZTEX USB-FPGA 1.15d LX-150 based, with a Cypress EZ-USB for flashing, feeding the FPGA with data and USB communication. Uses only one 24MHz oscillator, some schematics available on their site:
http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html
By the way the price of this one beats the Opal board I mentioned earlier. Got an email quote at a unit price of 357EUR, power supply not included.
The ZTEX USB-FPGA 1.15d LX-150 based, with a Cypress EZ-USB for flashing, feeding the FPGA with data and USB communication. Uses only one 24MHz oscillator, some schematics available on their site:
http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html
By the way the price of this one beats the Opal board I mentioned earlier. Got an email quote at a unit price of 357EUR, power supply not included.
I find it interesting because of the FX2 chip, but apart from that it has too much: extra DDR SDRAM, extra EEPROM, extra CPLD, microSD card slot. The pricetag is only a factor of 2 above what we hope to achieve (note that they are missing the power supply section and need 3 different voltage rails).
I don't know about the others, but I am in it for the fun of developing a board. The board you linked may be a very good start to get FPGA developers to write code, but once our board is go, it won't be cost effective (unless you figure their support and warranty are worth the price). I am not arguing against the board: it is good for early adopters, but eventually we should beat it.
For a clock source: you will probably need two: one for the FPGA, one for the MSP430. For the FPGA, I suggest the ASEM1-100.000MHZ-LC-T: it's small (3.2x2.5mm2) and should be sufficiently stable. For the MSP430, it seems a 25MHz source is needed, like the ASEM1-25.000MHZ-LC-T.
I am not very happy with using a "normal" crystal, because they are much larger then these SMD-MEMS oscillators. One question I am not sure of: can we maybe get away with feeding the FPGA only 25MHz? Then we could save one oscillator.
I am not very happy with using a "normal" crystal, because they are much larger then these SMD-MEMS oscillators. One question I am not sure of: can we maybe get away with feeding the FPGA only 25MHz? Then we could save one oscillator.
Consider this design:
The ZTEX USB-FPGA 1.15d LX-150 based, with a Cypress EZ-USB for flashing, feeding the FPGA with data and USB communication. Uses only one 24MHz oscillator, some schematics available on their site:
http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html
By the way the price of this one beats the Opal board I mentioned earlier. Got an email quote at a unit price of 357EUR, power supply not included.
Actually: what is the status on the MSP430 schematics? Which signals are used, which signal names (important for merging the designs)?
With blind vias it'd be easier to put gnd on the 2nd layer and route the gnd pins down to that, it's not strictly necessary though. Can you finish routing up the rest of the board? It's pretty close to done. Look in the main folder.
We still need a clk source and MSP430 hooked up. I've freed up 1 layer of the board, so that should make things easier. We'd need the FPGA and MSP guys to come in now and offer some input on how best which IOs go where and the clock source.
We still need a clk source and MSP430 hooked up. I've freed up 1 layer of the board, so that should make things easier. We'd need the FPGA and MSP guys to come in now and offer some input on how best which IOs go where and the clock source.
I may get to it tonight.
For a clock source: you will probably need two: one for the FPGA, one for the MSP430. For the FPGA, I suggest the ASEM1-100.000MHZ-LC-T: it's small (3.2x2.5mm2) and should be sufficiently stable. For the MSP430, it seems a 25MHz source is needed, like the ASEM1-25.000MHZ-LC-T.
I am not very happy with using a "normal" crystal, because they are much larger then these SMD-MEMS oscillators. One question I am not sure of: can we maybe get away with feeding the FPGA only 25MHz? Then we could save one oscillator.
[...]
I also agree the MSP should be powered by the power solution of the fpga.The level shifters would add adtitional parts and complicate things so we my use this in another version.
[...]
I also agree the MSP should be powered by the power solution of the fpga.The level shifters would add adtitional parts and complicate things so we my use this in another version.
[...]
Careful: you are killing one of the original features here: if the MSP is not powered from the USB connector, then it cannot enable or disable the power for the FPGAs. This was (at least for me) an important feature. And I don't see the problem, actually: you just need an additional small switcher that hangs on the USB power pin and outputs 2.5V. No reason to talk about level shifters or anything.
So you just call for an additional littel 2.5 V source just for the MCU in order to make it independent from the FPGA power supply? If thats teh case you are cerrtainly right. I thought you wanted to use an centrall power supply controler in addition.
Sorry for the misunderstanding.
With blind vias it'd be easier to put gnd on the 2nd layer and route the gnd pins down to that, it's not strictly necessary though. Can you finish routing up the rest of the board? It's pretty close to done. Look in the main folder.
We still need a clk source and MSP430 hooked up. I've freed up 1 layer of the board, so that should make things easier. We'd need the FPGA and MSP guys to come in now and offer some input on how best which IOs go where and the clock source.
We still need a clk source and MSP430 hooked up. I've freed up 1 layer of the board, so that should make things easier. We'd need the FPGA and MSP guys to come in now and offer some input on how best which IOs go where and the clock source.
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