Topic: Modular FPGA Miner Hardware Design Development - page 21. (Read 119276 times)

I'll be happy to produce the 1st ten boards for $0, just to get this project up and running and to debug/iron out any issues we might have. Just throw the blank PCB and parts in my direction and I'll get right to work.

At this point of time, it's more of a hobby/fun thing to do then monetary, perhaps later on I'll add a donation link or something somewhere. I hope to get 1 FPGA board myself to keep. As a start I think we need to figure out if the demand is there, so I hope this will help out. I will continue to support this for as long as I possibly can, and if at any time I feel I might not meet datelines and/or the demand is starting to pickup I'll update.

I'd hate to see this turn out into a Funcube Dongle, whereby the hardware is known to exist, but can't be bought because the demand exceeds supply. So yes, I'd say I'll stop at 50 boards, unless the demand is really trickling in and we want to keep production costs low.

So wich price you would project for such a DIMM board in production and soldering of one FPGA and the power supply and communication devices dicussed up to now, if we would decide to having you make them?
Up to now i considered Pcbcart (China) http://www.pcbcart.com/ to build and assemble this boards, but i havent asked for a price quote yet concerning the assembley(the board manufacturing would be ~350 Euro for 10 boards)

On the power question:

I ran the xilinx power estimator tool using a utilisation of 105% for all parts avaidable (Logic,DRAM,DSP,DCM,....).
It seems 5.5 W is the maximum the FPGA allows before getting cooked.
This splits to:

- 1.2 V :  4,2 A
- 2,5 V : 0,3A

This numbers heavily scale with temperature. So cooling is a major influence factor as power consumption ranged from 7.7W (no cooling, no heatsink, -T_case 125 °C)
to  4.5 W (500 LFM,huge heatsink,T_case 40°C) using the same setup.

This estmination should cover for the absolut possible maximum, but as i am totaly new to this tool i would like somebody more used to the FPGA design to confirm this results.



In addition it seems the MSP430F24xx is becoming a frequent number in this disscussion.
We should advance with our BUS deciscion anyway so please name more detailed setups on this one from now.

This project will be very lucky to have your help!

I'd like to add that if we were to populate the 1st few boards ourselves, before letting a board house do it, it'd be possible to test out the Vregs beforehand to make sure they work properly before putting down the $$$ FPGAs.

No problems with $160 ICs, so long as the board and part is dehumidified (I put them through an oven if I'm unsure, packing them properly with dessicant helps alot here), I can put them down properly. I have plenty of time till the end of the year to work on this at the moment, I agree that once production rates need to ramp up, it's be alot better to get it done professionally through a board house, but for the 1st few protos, I can volunteer to assemble them up. Even if the FPGAs were say pulled from a working board, I can also reball and solder them down to the new board (Not sure if we'll take this route).


I can easily do reflow on the back side of the board as well if the need arises, I personally hate QFN packages myself, some of them that have pads that don't wrap around to the top side are a pain to work on, you can't inspect them after you've soldered them down, and you're not always quite sure how much paste to apply on the centre pad.


Haha, not quite, I'm based in Singapore at the moment, so yeah my posting times might be alittle weird.

I think so, this MCU has 47 GPIO pins, so, I think it will be enough. Would someone be willing to make a table of all the expected signals needed? This could be for a tentative design including the maximum conceivable number of bus interfaces, so that we don't end up short later.


Great! Yes, we should share as much as possible. I wish there was a "GitHub" for Eagle files. Would a Dropbox shared folder work well?


I couldn't find any of the XC6SLX150-N3 at AVNET in the FGG484 package, not even listed. Maybe you get different results because you're in Europe?


Once again, the design of this board doesn't have to have any influence on future designs. If a second generation FPGA board is made with higher power requirements, the regulator will increase accordingly. This design needs to serve this FPGA. Period. You'll never get anywhere if you always try to plan for future designs.


I agree that this is the most pressing thing to know right now. I'll try to do this, but exactly what design are we using? Can we get a link to the code placed in the first post?


This would be very helpful! At least for the first prototypes. I looked through your blog and you look very experienced. How would you rate your confidence working with $160 ICs? How much time do you have to work on this? Nothing personal to you, but for a larger order on the scale of 50 boards, it would probably be faster and more reliable to go with a professional board house.


I agree, as long as we're not talking about only reflowable compenents, I would also volunteer to solder them by hand. I've actually done a batch of boards this way in the past: had the QFN ICs reflowed by the board house and then did all the rest of the soldering myself (I don't do reflow, yet).

Sorry for the very long post, there were a lot of new posts to respond to when I woke up! I'm guessing most of you must be in Europe, or insomniacs 

A side-note, check out this little beast:

Algorithm accelerator:
http://www.dinigroup.com/new/DNBFC_S12_PCIe.php
Featuring 12 LX-150's + LX-150T, on a PCI-E board, independently powered (consumes up to 75W, PCI-E independent power just like a GPU).


Pricetag... around 10k USD, so around $833 per FPGA chip.
Power draw - 6.25W per FPGA+DDR3 chip (assuming only the LX-150's are very active).

Posting as food for thought, could be considered as a price and design reference point, esp. given the fact that it uses the same FPGA.

6.25W power draw, at 1.2V = 5.2Amps not counting conversion and ohmic losses.

Hi guys, I have access to BGA rework/repair equipment, if a prototype batch needs to be made, say about 50 boards max, I can assemble and test them out.

http://fillwithcoolblogname.blogspot.com/

That's my blog. I usually do Xbox 360 reballs. I'm new to the bitcoin scene, but not new to electronics.

At this point I think we just need to iron out the PSU requirements, and then design a board to fit all this in. Once that's done we can start drawing up a schematic and then try routing a board that'll fit (and is not too expensive), whilst the bus decision is being finalised. As for populating the backside, I don't think that's a major problem, if cost is prohibitive I figure we can manually solder them on by hand (if the components are say decoupling capacitors and sockets.). just my 2cents.

Is there any indication that 10A are needed? My understanding is that the maximum that the chip may use is 5A. Can someone run a power-analysis, assuming a 100% state-change rate for all flip flops? The data-sheet unfortunately does not specify a safe maximum current.

As for 2.5V: we probably consume most for the VCCaux net. We have just a hand full of connections on bank 2. But again: for correct numbers we need to run the actual design through the power-analysis.

5 Amps on 1.2V? No way. If we want this thing to operate stable and have some headroom for future designs, we should allow more like 10A per FPGA. The regulator you linked can supply 12A, so one of those for each FPGA might be a bit overpowered, but one for both won't work. In that case you'll need to use a bigger one (>18A).
Do we have some data on the actual power consumption on the 2.5V rail?

I would opt against this. Having SMD components on the backside increases the manufacturing cost a lot. You need a second mask for the solder paste made and (some?) manufacturers charge extra for dual side population of the board. As for necessity: the Xilinx UG393 "Spartan-6 FPGA PCB Design and Pin Planning Guide" states under "PCB Capacitor Placement and Mounting Techniques", "0402 Ceramic Capacitor" that for thicker PCBs (>1.575mm) the best placement is the top surface. While for thinner PCBs the bottom side is suggested, I would not fret about that so much. The usual PCBs (especially when multi-layer) are right on that border of thickness, so both placement options must be sub-optimal... Anyway: only the VCCint capacitors are any important; we barely use any of the banks and VCCaux should be low current.


We should postpone this selection until someone can give more definite numbers on the current we will need. So can someone compile a core with some interface logic and then look up the power consumption from the PowerPlanner?


One will be plenty.

I still think orienting the USB socket to face the PCB makes things difficult for the user: they have to take a USB cable and cut away half the plastic on the plug. Otherwise, they will not be able to get the plug into the socket.

How about putting the USB socket on the edge of the board, but facing sideways. Then the locking handles of the DIMM socket can prevent plugging in a USB cable.

The two squares are the voltage regulators (LTM4601EV-1#PBF) that TheSeven suggested. I initially considered the SimpleSwitcher series from National Semiconductor, which are cheaper. But they also need more external components, apparently. I am not convinced which is the better choice, at the moment.

EDIT:
And I agree on the mounting holes: I forgot them in my sketch of a board.


Currently, Avnet has 344 of the FGG484 packages in stock and 0 of the CSG484 packages.

Maybe just to remember you.

We wanted to use a Molex AND a barrel connector.Of course this will result in some space issues.
The backside will be populated with condensators anyway so we might use it also for some other parts.

I guess we will have to increase heith of the DIMM anyway.

Regarding Voltage supply there were seriously considered (for the FPGA supply):

For 1.2 V http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=LTM4601EV-1%23PBF-ND    5A @ 1.2V

For 2.5V ( multiple of) http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=R-78AA2.5-1.0SMD-ND 1.9A @ 2.5V


Just out of interest. Will one Msp 430 be sufficient for both FPGA's ?  

PS.:
Today i will also start a rough layout in eagle.Maybe we could share eagle files for comparison.

Yeah, and more powerful ones generally need more space, so you should account for that
And I'd really suggest to put the USB connector below the power connector, facing downward, to have a mechanical protection from connecting multiple hosts. In this design this even seems to be better from a space point of view.

I knew someone was going to point out those regulators... I just wanted to put something there as an idea for the space needed.


What are the two squares to the left of the FPGAs? Also, an important thing is missing from this sketch: mounting holes! This will be very important when not using the motherboard.

I didn't notice the difference in availability, but a larger pitch makes a lot of things easier, including assembly, so I would suggest going with the larger package.

I don't think linear regulators with 100mA output current are going to cut it. A reference picture using two CSG484 was posted some time ago. That still used the smaller FTDI chip, though.


As for routing: I am currently trying to route an FGG484 package, but less because of the routing constraints but because of the availability (FGG is much easier to get than CSG).

I wanted to get an idea what the space would look like on this board. This shows two LX150s in the FG484 package and the MSP430 in the QFN64 package. This FPGA is available in a smaller package, CSG484, but I think this one fits nicely, and a larger pitch means easier job routing the signals to the pins. For comparison, this package is 23 mm square, the smaller one is 19 mm square.

I don't think there is much reason to discuss other FPGAs here. This board will have the Spartan-6. If someone wants to make a board with a different FPGA later, nothing is stopping them from using a different MCU or different method of interfacing with the bus entirely. The daughterboard is self contained, it just needs to conform to the specifications of the DIMM connector and bus interface, so that it's compatible with the motherboard.

I see now what you mean. The MSP430F5528 has built in level shifting for the USB lines, meaning the MCU will run at 2.5V, but shift the USB I/O up to 3.3V by means of a built in LDO on the USB input voltage. That seems like the ideal behavior for us. As long as someone else is willing to work on the firmware for this, I think it will be a good MCU for this design.