Jay we are back to the power supply disscussion.
I think everything has been already said why we have choosen a 12 V - 20 V input net ( less current, wide range input for ATX PSU und Laptop supply......)
TheSeven,serveral other people and also i, have posted a variety of voltage regulators fit for our application (11-20V input 1,2 V and 2.5 V output) so i consider this problem solved.
Therefore we can go on with the BUS design and FPGA routing.
I started reading through the documentation of the Spartan 6 and the MSP430f55xx series for my routing.
Has anybody got a more or less complete overview over the pins we need to use on the FPGA and what is to be done with I/o pins not needed ?
Topic: Modular FPGA Miner Hardware Design Development - page 20. (Read 119320 times)
My concern is not just with efficiency, but with the high price of those switching regulators. $20 per FPGA is really a significant cost, even higher than the PSU I linked which could supply 10 FPGAs! If we limit the design to not allow laptop adapters, we could potentially reduce the cost.
I haven't read through datasheet completely yet, but the TPS40041 is only $3 and has 90% efficiency. Short summary: 2.25V to 5.5V input, 15A output.
I haven't read through datasheet completely yet, but the TPS40041 is only $3 and has 90% efficiency. Short summary: 2.25V to 5.5V input, 15A output.
This is just a switching regulator controller, which needs several external components, which will definitely cost more than this chip itself. This will also probably need more board space, and you can do much more wrong during the PCB design. The efficiency numbers are probably calculated for a very expensive choice of external components, so this doesn't really sound good to me.
One question, why are we planning for 12V input when we want 2.5V maximum? Wouldn't it be much more efficient to be regulating the 5V rail off of an ATX power supply? For reference, this power supply has a 34A limit on the 5V rail (170W) and is only $16. Actually, it also has 28A on 3.3V (92.4W), which might be useful too. Trying to step down 12V to 2.5V is going to be very wasteful.
It seems like as PSUs get more expensive, they are only increasing the 12V rails, so we could save a lot of money by using these cheap PSUs with low 12V rails.
It seems like as PSUs get more expensive, they are only increasing the 12V rails, so we could save a lot of money by using these cheap PSUs with low 12V rails.
The PSU you quoted provides more power on the 12V than on the 5V rail. The 5V and 3.3V usually have a total power limit for both of them combined, which is only slightly above the 5V limit. Also, when paying thousands of dollars for FPGAs, you won't really mind paying $20 more for a better, more efficient PSU. These cheap PSUs are usually crap efficiency-wise. However, the one you quoted can easily run more than 10 FPGAs on its 12V rail.
When talking about regulator efficiency, you aren't considering cable and connector resistance/voltage drops and current limits. I'm fairly sure that a 12V PSU design will run more efficient than a 5V design. If the regulator we choose can accept lower voltages as well, that would of course be even better. But I'm not sure if there are cheap and efficient 1.2V regulators with a very wide 3.3-20V input voltage range.
One question, why are we planning for 12V input when we want 2.5V maximum? Wouldn't it be much more efficient to be regulating the 5V rail off of an ATX power supply? For reference, this power supply has a 34A limit on the 5V rail (170W) and is only $16. Actually, it also has 28A on 3.3V (92.4W), which might be useful too. Trying to step down 12V to 2.5V is going to be very wasteful.
It seems like as PSUs get more expensive, they are only increasing the 12V rails, so we could save a lot of money by using these cheap PSUs with low 12V rails.
It seems like as PSUs get more expensive, they are only increasing the 12V rails, so we could save a lot of money by using these cheap PSUs with low 12V rails.
The community has already decided to include the option of using laptop power supplies (that run anywhere from 12 to 20V) to power the design, electrically it might not seem like the best of all ideas, the higher input voltages usually mean a lower efficiency. With the reg I have in mind, even at 16V in we'd be getting around 70ish % efficiency, not too shabby. Transient and ripple also look good (at least in the datasheet, layout and parts will have an impact).
It's not a bad thing to have, a person aiming for max efficiency has the option to go out and get a suitable adapter that'll get you better efficiency figures.
My concern is not just with efficiency, but with the high price of those switching regulators. $20 per FPGA is really a significant cost, even higher than the PSU I linked which could supply 10 FPGAs! If we limit the design to not allow laptop adapters, we could potentially reduce the cost.
I haven't read through datasheet completely yet, but the TPS40041 is only $3 and has 90% efficiency. Short summary: 2.25V to 5.5V input, 15A output.
One question, why are we planning for 12V input when we want 2.5V maximum? Wouldn't it be much more efficient to be regulating the 5V rail off of an ATX power supply? For reference, this power supply has a 34A limit on the 5V rail (170W) and is only $16. Actually, it also has 28A on 3.3V (92.4W), which might be useful too. Trying to step down 12V to 2.5V is going to be very wasteful.
It seems like as PSUs get more expensive, they are only increasing the 12V rails, so we could save a lot of money by using these cheap PSUs with low 12V rails.
It seems like as PSUs get more expensive, they are only increasing the 12V rails, so we could save a lot of money by using these cheap PSUs with low 12V rails.
The community has already decided to include the option of using laptop power supplies (that run anywhere from 12 to 20V) to power the design, electrically it might not seem like the best of all ideas, the higher input voltages usually mean a lower efficiency. With the reg I have in mind, even at 16V in we'd be getting around 70ish % efficiency, not too shabby. Transient and ripple also look good (at least in the datasheet, layout and parts will have an impact).
It's not a bad thing to have, a person aiming for max efficiency has the option to go out and get a suitable adapter that'll get you better efficiency figures.
One question, why are we planning for 12V input when we want 2.5V maximum? Wouldn't it be much more efficient to be regulating the 5V rail off of an ATX power supply? For reference, this power supply has a 34A limit on the 5V rail (170W) and is only $16. Actually, it also has 28A on 3.3V (92.4W), which might be useful too. Trying to step down 12V to 2.5V is going to be very wasteful.
It seems like as PSUs get more expensive, they are only increasing the 12V rails, so we could save a lot of money by using these cheap PSUs with low 12V rails.
It seems like as PSUs get more expensive, they are only increasing the 12V rails, so we could save a lot of money by using these cheap PSUs with low 12V rails.
A bit off topic, but has anybody though about simply using Arduino http://arduino.cc/en/ together with an Ethernet shield http://de.rs-online.com/web/cpd/6961661/ and then just making one new shied for every FPGA that shall be plugged on top?
This could be the 100€ "backplane" with Ethernet and each FPGA board would need nothing than the FPGA and power. This could also keep the cost of the daughterboard low.
This could be the 100€ "backplane" with Ethernet and each FPGA board would need nothing than the FPGA and power. This could also keep the cost of the daughterboard low.
Well just to explain this again maybe. The consuption of 7.7 W is calculated for a temperature of 125 °C wich would absolutly certain result in a total destruction of the IC.
The last value that would be usable would be at 85 °C an there i got those 5,5 W.
This regulator here, same series as you posted, but would offer up to 15 A at 1.2V wich should be enough for two fpga's in our current setup. http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=LTM4627EV%23PBF-ND
This would give us ~7 A per FPGA minimum resulting in a 65% overhead over my calculation. And for the first DIMM's we will use only one FPGA anyway so there should be plenty of security and the chance to measure the real values.
The last value that would be usable would be at 85 °C an there i got those 5,5 W.
This regulator here, same series as you posted, but would offer up to 15 A at 1.2V wich should be enough for two fpga's in our current setup. http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=LTM4627EV%23PBF-ND
This would give us ~7 A per FPGA minimum resulting in a 65% overhead over my calculation. And for the first DIMM's we will use only one FPGA anyway so there should be plenty of security and the chance to measure the real values.
Maybe we can simplify even further for prototyping by using National's simple switchers, eg the LMZ22010
http://www.national.com/pf/LM/LMZ22010.html#Overview
This reg uses very few external parts, houses an internal shielded inductor, each puts out 10A and we can place each part near the FPGA for easier routing/decoupling. The only con I guess is the slightly higher cost per part.
*edit I've looked at digikey pricing, and it doesn't seem all that far apart if we use 2x 8A parts (each feeding the FPGA), I think we need to seriously come up with some reliable power consumption figures, anyone with a demo board/dev kit want to confirm the figures for us? That'd be a great help.
There you have 7.7W, which is ~6.5A, which already exceeds the 12A max for two FPGAs. Also, please don't trust those tools. They're estimating something like 3 watts for my virtex 5 design, and judging from the amount of heat generated the real power dissipation must be way higher. You're only really safe if you assume 100% of the gates toggling on each clock cycle. SHA256 is surprisingly close to that...
Well just to explain this again maybe. The consuption of 7.7 W is calculated for a temperature of 125 °C wich would absolutly certain result in a total destruction of the IC.
The last value that would be usable would be at 85 °C an there i got those 5,5 W.
This regulator here, same series as you posted, but would offer up to 15 A at 1.2V wich should be enough for two fpga's in our current setup. http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=LTM4627EV%23PBF-ND
This would give us ~7 A per FPGA minimum resulting in a 65% overhead over my calculation. And for the first DIMM's we will use only one FPGA anyway so there should be plenty of security and the chance to measure the real values.
@TheSeven : Maybe you also run some esteminations regarding power consumption as you are more experienced with FPGA design than me.
I thought about the FPGA signals some more and edited my previous table: PROGRAM_B should be dedicated (like SSEL) to be able to reboot each FPGA individually.
You can also click the middle mouse button when routing.
I routed some part of the bus system so far.
As im new to the eagle software its hard getting used to alle the tricks you need.
The way the parts library is organised and the issues im having with changing layers are really hard to come by.
Does anyone know a more punctual way to change layers ?
As im new to the eagle software its hard getting used to alle the tricks you need.
The way the parts library is organised and the issues im having with changing layers are really hard to come by.
Does anyone know a more punctual way to change layers ?
LAYER
5 Amps on 1.2V? No way. If we want this thing to operate stable and have some headroom for future designs, we should allow more like 10A per FPGA. The regulator you linked can supply 12A, so one of those for each FPGA might be a bit overpowered, but one for both won't work. In that case you'll need to use a bigger one (>18A).
Once again, the design of this board doesn't have to have any influence on future designs. If a second generation FPGA board is made with higher power requirements, the regulator will increase accordingly. This design needs to serve this FPGA. Period. You'll never get anywhere if you always try to plan for future designs.
When saying "future designs" I was talking about FPGA designs which might use more power than the current, not really optimized versions for that chip do. I'd rather spend $5 more on voltage regulation than having unstable boards in the end.
So I'd say that the power supply should be designed to be able to easily handle the absolute maximum possible power consumption of the FPGA, and also have some headroom, as usually both efficiency and regulation stability decrease at nearly full load of the voltage regulator. Targeting 80% maximum load might be sensible.
On the power question:
I ran the xilinx power estimator tool using a utilisation of 105% for all parts avaidable (Logic,DRAM,DSP,DCM,....).
It seems 5.5 W is the maximum the FPGA allows before getting cooked.
This splits to:
- 1.2 V : 4,2 A
- 2,5 V : 0,3A
This numbers heavily scale with temperature. So cooling is a major influence factor as power consumption ranged from 7.7W (no cooling, no heatsink, -T_case 125 °C)
to 4.5 W (500 LFM,huge heatsink,T_case 40°C) using the same setup.
This estmination should cover for the absolut possible maximum, but as i am totaly new to this tool i would like somebody more used to the FPGA design to confirm this results.
I ran the xilinx power estimator tool using a utilisation of 105% for all parts avaidable (Logic,DRAM,DSP,DCM,....).
It seems 5.5 W is the maximum the FPGA allows before getting cooked.
This splits to:
- 1.2 V : 4,2 A
- 2,5 V : 0,3A
This numbers heavily scale with temperature. So cooling is a major influence factor as power consumption ranged from 7.7W (no cooling, no heatsink, -T_case 125 °C)
to 4.5 W (500 LFM,huge heatsink,T_case 40°C) using the same setup.
This estmination should cover for the absolut possible maximum, but as i am totaly new to this tool i would like somebody more used to the FPGA design to confirm this results.
There you have 7.7W, which is ~6.5A, which already exceeds the 12A max for two FPGAs. Also, please don't trust those tools. They're estimating something like 3 watts for my virtex 5 design, and judging from the amount of heat generated the real power dissipation must be way higher. You're only really safe if you assume 100% of the gates toggling on each clock cycle. SHA256 is surprisingly close to that...
I routed some part of the bus system so far.
As im new to the eagle software its hard getting used to alle the tricks you need.
The way the parts library is organised and the issues im having with changing layers are really hard to come by.
Does anyone know a more punctual way to change layers ?
As im new to the eagle software its hard getting used to alle the tricks you need.
The way the parts library is organised and the issues im having with changing layers are really hard to come by.
Does anyone know a more punctual way to change layers ?
[...]
Olaf.Mandel, is a FT2232 still necessary if we use this MCU? Is the point to avoid having to bit-bang JTAG with the MCU? Or are you only talking about on the motherboard?
Olaf.Mandel, is a FT2232 still necessary if we use this MCU? Is the point to avoid having to bit-bang JTAG with the MCU? Or are you only talking about on the motherboard?
No, the MCU replaces the FT2232. The MCU could be used both on the DIMM and (with a different firmware!) on the "dumb" motherboards.
As for bitbanging: you should probably do it, as it would be completely unreasonable to add an extra chip (that costs nearly as much as the MCU!) to the boards just to avoid bitbanging. It is a bit of a hassle to code, and it can be slower than a hardware engine, but: it should be doable with just the MCU.
I am currently (trying) to rout a layout using the MSP430f5509 wich should be enough for our purpose or am i mistaken here ?
I just hat a look into the MSP430F4210 documentation and found it not to support USB.
Seems the MSP430F5504 would support USB,SPI and JTAG so it houses all Bus protocols we currently seem to desire on the DIMM.
Seems the MSP430F5504 would support USB,SPI and JTAG so it houses all Bus protocols we currently seem to desire on the DIMM.
The part number I heard was MSP430F5528, although I think any of the F551x or F552x would be fine. Let's try to pick one in a QFP package as opposed to a QFN, as li_gangyi suggested. Is anyone volunteering to lead the programming effort for this MCU?
Olaf.Mandel, is a FT2232 still necessary if we use this MCU? Is the point to avoid having to bit-bang JTAG with the MCU? Or are you only talking about on the motherboard?
Quote
This would be great. Do i understand correctly; you would assemble the boards, but we are going to have the PCB manufactured somewhere else ?
Yup, that's right, not currently equipped out at the moment to do PCBs professionally (I can only do double sided). Certaintly something we do not want to skimp on, a good quality properly routed board will make or break the prototyping stage, the layout can be optimised later to be more cost effective. I'd like to, at least for the start, not use any parts smaller then 0603 if there's no real need to, and reduce the use of QFNs, they're harder to inspect visually, and the foot print is not much bigger for QFP parts, neither is it really cheaper.
[...]
I think so, this MCU has 47 GPIO pins, so, I think it will be enough. Would someone be willing to make a table of all the expected signals needed? This could be for a tentative design including the maximum conceivable number of bus interfaces, so that we don't end up short later.
I think so, this MCU has 47 GPIO pins, so, I think it will be enough. Would someone be willing to make a table of all the expected signals needed? This could be for a tentative design including the maximum conceivable number of bus interfaces, so that we don't end up short later.
This is the on-DIMM connection I am working on in my design (not ready for showing, yet; maybe during the weekend). Given are all signals going from the head (FT2232, MSP230, DIMM connector, ?) to the FPGAs:
Edit: Changed topology of PROGRAM_B.
| Name | Dir. | Top. | Term. |
| TCK | in | star | (thev.) |
| TMI | in | star | (thev.) |
| TDI | in | ring | - |
| TDO | out | ring | - |
| SCLK | in | star | thev. |
| SSEL | in | dedi. | - |
| MOSI | in | star | (thev.) |
| MISO | out | star | (pull.) |
| PROGRAM_B | in | dedi. | - |
| (DONE) | out | star | pull. |
| CLK | in | star | thev. |
| (IRQ_B) | (in/)out | star | pull. |
Direction is as seen from the FPGAs ("input" into FPGAs, "output" from FPGAs, ...). Topology is either star, ring (TDO connected to TDI) or dedicated. Termination is per DIMM and can be either a Thevenin Termination with two 100R resistors (see UG380), a pullup resistor of 4k7 or nothing. Features put in brackets are optional.
The "trick" is to connect the SPI interface to the pins used for loading the bit-pattern. This allows loading the FPGA without using the JTAG interface. This is why IRQ_B can be an input: it is during parts of the configuration process. The IRQ signal suggested here is shared between all FPGAs: there shouldn't be so many that this starts becoming worrisome. The connections are then:
| Name | FPGA-Pin |
| SCLK | CCLK |
| MOSI | DIN |
| IRQ_B | INIT_B |
[...]
I couldn't find any of the XC6SLX150-N3 at AVNET in the FGG484 package, not even listed. Maybe you get different results because you're in Europe?
[...]
Currently, Avnet has 344 of the FGG484 packages in stock and 0 of the CSG484 packages.
I couldn't find any of the XC6SLX150-N3 at AVNET in the FGG484 package, not even listed. Maybe you get different results because you're in Europe?
[...]
No, I was talking about the -3, not the -N3 variant. The -N3 isnot in stock anywhere (I found). The trick is: you can do the prototypes with the -3 and pay a bit more and have the large run made with -N3 FPGAs.
I just hat a look into the MSP430F4210 documentation and found it not to support USB.
Seems the MSP430F5504 would support USB,SPI and JTAG so it houses all Bus protocols we currently seem to desire on the DIMM.
@li_gangyi
This would be great. Do i understand correctly; you would assemble the boards, but we are going to have the PCB manufactured somewhere else ?
Seems the MSP430F5504 would support USB,SPI and JTAG so it houses all Bus protocols we currently seem to desire on the DIMM.
@li_gangyi
This would be great. Do i understand correctly; you would assemble the boards, but we are going to have the PCB manufactured somewhere else ?
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