Topic: Modular FPGA Miner Hardware Design Development - page 19. (Read 119320 times)

Just to get an update.

Since dicussion almost cheased on this.  Is it decied to use SPI  I2C and USB on the bus or have there been any further ideas or objections.?


Maybe you could give some feedback so we may create a standardfor our PCB layouts.

size:133mmx60mmx1,25mm DIMM standart 240 pins DDR3

4 layers

cooper thikness: 35um min , may be increased for high current rails (1,2V) 

Where are we going to share future files ?

Do we use my dropbox or someones github? 

In Eagle, the different sheets have no connectors like in Altium. You cannot get a symbol that stands for a full sheet like in Altium to do overview diagrams with detailed schematics in different sheets. Also, I used connection symbols in my design, but be aware: they are only decorative and do absolutely nothing!!! The connection between different sheets is done only through the name of the nets. That is why I put labels on the different nets, to keep track of what goes where. So all nets that have a dedicated name (changed from N$?? to something else) will be connected when you copy the sheets. I think (please verify this!) that the different unnamed nets (N$??) get renumbered if you paste new stuff. But if they are not, then this can get really ugly...

I discovered this one here http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail&name=LTM4627EV%23PBF-ND

I could provide  the 1.2 V rail for both FPGA's with a safe overhead.
A second one with less power could serve the 2.5 V rail for both FPGA's.
So those are my favorite ones.

I would appreciate it if you could do the power supply design.
remember :

Input 11-20V
Molex 8981
Barell 2.5mm
110 pins ground plus 110 pins 12V on the DIMM pins

~6,5 A @ 1.2 V for one FPGA

~? A @ 2,5V

So you may do the "Power supply" sheet.
Is there any way to piece different sheets together ?

They also accept Eagle files, so no need for exporting anything.


I just checked: you are right, the default is pull down, pull up or floating is an option. The reason why I thought the default was pull up is the HSWAPEN pin: it enables pull ups during configuration. So during configuration, the choice is between pull up and floating. So there are several options:

• All pins connected to VCCIO:
  
  • Program pull ups in the bitstream: should work nicely.
  • Leave bitsream at default pull-down: quite a power consumption during operation (bad choice).
• All pins connected to GND:
  
  • Program pull ups in the bitstream: quite a power consumption during operation (bad choice).
  • Leave bitsream at default pull-down: quite a power consumption during configuration.

As long as the signal names are correct, you can merge files, it is just very cumbersome:

• Open the first file, on the first sheet
• GROUP all
• CUT (0 0)
• Open the second file, create a new sheet or go to the sheet where you want to place stuff.
• PASTE, find a spot to place stuff (e.g. (0 0))
• Save file.
• Repeat for all sheets in the first file.

The above procedure has a minor fault if ICs are spread over more than one sheet (like in my design): once an IC is already present in the design, pasting in more gates of that IC will instead cause a new IC to be instantiated. You need to repair this manually, e.g.:

• For each gate that has the wring IC name:
• DELETE the gate
• INVOKE the gate from the original IC
• Place that gate at the position where the old one was: the connections are made automatically.

Seems thats what i get for writing to long posts. 

• What is the pcbcart default layer stack? Alternatively: what is a good layer stack we should specify?
• What does pcbcart mean when they ask for the "Min. Annular Ring"? The width of the ring on one side ((D_via-D_hole)/2) or the sum of the width on both sides of the hole (D_via-D_hole)? -> annular ring specifys a radius measure so annular ring(0,2mm)+drill radius(0.1mm) results in a minimum total diameter of 0.6mm,  objections ?
• What does "Impedance Control" mean in this context? A better selection of the board stock?
• I went with the "Lead Free HASL - RoHS" surface finish. Other suggestions? -> I was told Gold finish is suited better for BGA it would increase the total price by 15$
• Do you want to order the prototype from there, too? The minimum lead time of 12 working days plus shipping time translates to waiting three weeks for the board.-> you have got a point there, but i prefere the unbeatable price and industry quality over a quick delivery

All in all: we should probably finalize PCB specs (see below), so people can do the FPGA routing. This is nearly independent of the interface logic and power supply, but changing the specifications means having to redo a lot of the work. I would like to know:

• # of layers -> 4 to minimize board size
• thickness of copper for each layer -> im not an expert on this but ground and 1.2V will need 70um or more to allow narrow lines
• min trace width -> in acordance with the pcbcart requirements 0,2mm
• min space between things -> in acordance with the pcbcart requirements 0,2mm, might be reduced if needed for wiring between the FPGA pins
• min drill size -> in acordance with the pcbcart requirements 0,2mm
• min annulus -> in acordance with the pcbcart requirements 0,2mm

Ok, so I can reduce the size of the pads in my library. I wanted to say that then the 8mil trace will "just" fit between two pads. Unfortunately, I didn't think straight: (pad diameter) + (trace width) + 2*(min clearance) = 0.4mm + 8mil + 2*8mil = 1.0096mm > 1mm = (pad spacing). So it "just" does not fit.

Which is the better of the two options?

• pad=0.5mm, trace=6mil, clearance=6mil
• pad=0.4mm, trace=8mil, clearance=6mil

For the routing, it makes no difference, but I planned on either having VCCAUX=VCCIO=2.5V or 3.3V. I strongly prefer 2.5V, as that reduces the power consumption of the FPGA. In all cases, VCCINT=1.2V.

When you design the power supplies, I found the National Instruments webbench very helpful: it spits out schematics, full BOMs, the works. It even claims to know the maximum required current for the FPGA. Just disable the other three banks, as they should a´only draw minimal current (so only one VCCIO load, not four). But the Linear Technologies switcher we discussed recently is also nice (if pricey).

Yes, i did so two:) they also have a very good and fast support.

I have contacted them already they would also give us a price quote if we send some gerber files of a nearly final design and a BOM so they would also do the assembley.

Currently i am modifying your layout and routing to fit a 4 layer PCB.  Acording to my knowledge alls unused IO pins are bound to ground by default so i changed this in your schematic.(please someone verify this).
I added the MSP430 and will custom build the voltage regulators and add the power connectors.

Saddly i asume there is no way to merge the egale layout files automatic.(this used to be a lot easier with Altium.... I am totaly new to Eagle) And the library of eagle is confusing me over and over again.

We should define some fix dimensions and global rail namings to be abled to on this side by side.

Board : 133mmx60mmx1.25mm (DIMM standart with increase heigh)
4 layers
 
Vccint: 1.2V
Vccaux: 2.5V
Vccio:2.5V

I registered with pcbcart now, and my concerns about min wire thickness and distance are put to rest: you can specify many different combinations. Also: their 4-layer is nearly as cheap as the 2-layer board, so there is not much point going two-layer (I was used to having to pay much more for 4-layer boards because of the extra manufacturing steps).

But can someone answer me these questions:

• What is the pcbcart default layer stack? Alternatively: what is a good layer stack we should specify?
• What does pcbcart mean when they ask for the "Min. Annular Ring"? The width of the ring on one side ((D_via-D_hole)/2) or the sum of the width on both sides of the hole (D_via-D_hole)?
• What does "Impedance Control" mean in this context? A better selection of the board stock?
• I went with the "Lead Free HASL - RoHS" surface finish. Other suggestions?
• Do you want to order the prototype from there, too? The minimum lead time of 12 working days plus shipping time translates to waiting three weeks for the board.

All in all: we should probably finalize PCB specs (see below), so people can do the FPGA routing. This is nearly independent of the interface logic and power supply, but changing the specifications means having to redo a lot of the work. I would like to know:

• # of layers
• thickness of copper for each layer
• min trace width
• min space between things
• min drill size
• min annulus

The solder pad itself can be .4mm, but the solder mask clearance around the pad should be .5mm. We should be able to easily fit the design into 4 layers, 2 for power and ground planes.

Again I can assemble the prototype boards for close to nothing. We can decide on this later when the design is finalised.


What kinda voltages are we planning to use for the various rails? Perhaps I can start on the power supply design.

The copper thickness can be selected: very good, we may need more than the 35µm default. The 8mil minimal via diameter is even better (though you get less current through a smaller via)! The 8mil line width and line spacing are a problem, though: I cannot get an 8mil wire between two pads of the FPGAs: the clearance is too small. This problem can be solved by using more vias and routing everything on the other layers, but is is less than ideal.

There are "special PCBs" on the pcbcart webpage, though: 4mil for both specs. And they offer much more copper! I wonder how much that costs?

The point I made about the clearance depends on which pad diameter you use. My library used 0.5mm pads, but I read somewhere that 0.4mm may be sufficient. Any insight?

The thickness of 1.2mm is correct: the supplier I mentioned would have created a board with 1.6mm thickness which is too thick or with 1mm thickness, which is too narrow. The price of your manufacturer sounds very good: do you know someone who can do the soldering?


I just needed someone who gives me an online-quote. I was not looking at a specific country at all.


I used 120x65 mm². That is just the size of the demo, unrelated to an actual DIMM.


When I wrote that placing them on the front or back makes not much difference according to UG380, I was thinking of a 1.6mm board. I forgot the DIMM-connector, which needs a 1.27mm board. In that case, caps on the backside do seem to make more sense.

I had a qoute from pcbcart for a 4 layer board of our size with gold finish and 240 connection pinns for the DIMM ind 1.2 mm thikness resulting in 18 euro per board  for a quatity of 10 boards.

I would like to avoid manufayturing the boards in germany. The liddle to no increase in quality often doesn't justify the price over the asian manufacturers in my experience.

@Olaf.Mandel:

Wich size of the board did you set for your design and your quote ?

I tought of increasing the heith  of the daughterboard above standart DIMM size to 50 maybe 60mm to get more space.

I also think we will have to populate the backside with capacitors anyway.The Xilinx docu tells to put the smallest capacitors right behind the Vint and Vcc vias.
So having to additional layers for ground and signal would be a  plus.

Edit: just to have a frame of capabilitys we are talking about here. The restictions published by pcbcart:

Layers                         1-10 layers
Material                         FR4
Copper Thickness         1/2 to 2oz  (18um-70um)
Board Thickness         .016-.126"  (0.4mm-3.2mm)
Surface finish                 HASL,Ni/Au,OSP
Soldermask                 LPI, different colors
Board Dimension         600x700mm
Min Hole Diameter         8mil (0.2mm)
Min line width                 8mil (0.2mm)
Min line spacing          8mil (0.2mm)
Min SMT pitch             16mil (0.4mm)
Min. Annular Ring         .008" (0.2mm)
Aspect Ratio                 5:1
Surface/hole plating         ave. 25um min. 20um
Tolerance:    
Hole Tolerance (PTH)      .002" (0.05mm)
Hole Tolerance (NPTH)    .003" (0.075mm)
SM Tolerance (LPI)        .003" (0.075mm)
Dimension                .004" (0.1mm)
Electrically test                10V-250V, flying probe or testing fixture
   
   
   
 

I stated two prices: for one board it is 188EUR, for 50 boards it is 12.72EUR per board. Those are, of course, without the cost for the parts: one FPGA costs 112EUR, so getting two plus the word for even 188EUR would be quite a bargain, lt alone the 12.72EUR price tag.   


2-layer to 4 layer is a question of price and size: the 2-layer board is cheaper per area, but it is also larger. And the board may grow so large in the 2-layer design that it is too high or too wide for our preferences. Comments?

About the vias: probably. I used multiple vias, where possible, also. I may even add a few more below the centre of the FPGA, to not let the traces get so hot.

The prices for populating are for 1 board? That price is inclusive or exclusive of the parts cost? It may be necessary to goto a 4 layer board, and then put the regs and decoupling caps on the backside. We're probably gonna have problems routing the LTM4627 output traces for 10+A without multiple vias that conduct to a power + ground plane.

I did a demo of two FPGAs connected by JTAG and SPI. The SPI is connected to the pins used during configuration, so the chips can also be booted from there. The board is two-layer only and uses rather normal specifications, so it should be to make. The problem with that is: the board becomes large because of the high-current busses (see top of board).



Full files at: the Github repository, in the slx150x2 / hw directory.

Current todo:

• There is a choke point in the bottom layer, in the middle of each FPGA. The polygons are too small for 5A+ of current. This can be fixed by routing VCCaux across some unused pins. Will do that tomorrow.
• Check the design! I may be completely out to lunch.
• My understanding was, that the default behaviour of ISE is to pull unused pins up to VCC_O . That is how I connected most pins. If it is pulldown to GND, the design needs to change quite a bit...

As for manufacturing cost: PCB-Pool (a German PCB maker, they populate boards too) shows these prices (they are not really cheap, but it may be Ok for prototyping):

Edit 2:
For 1 board with solder-stop, silkscreening, E-test, 120x65 mm²: 81EUR
For populating that board with 63 SMD parts: 188EUR
Both prices are without tax.

Edit:
If the board had components on the backside, also, the price for populating the board rises to 263EUR.

Edit 3:
Just to put this into perspective: if you order 50, not 1 PCBs, then the per-PCB cost is 10.16EUR + 12.72EUR, so only 10% of the FPGA costs.

I just created a dropbox folder for sharing and collecting als data needed for this development from now on.

Please give me a pm with your email adresse in case you want to upload something and have a dropbox account so i may add you to the group. https://www.dropbox.com


@mamok:   Thanks,  so it seems its best to just leave them alone/unconnected 

I think Xilinx's tools default to creating bitstreams that pull down unconnected pins to ground. Not sure what happens if you try and connect them to a different voltage externally, but finding out probably wouldn't be the best idea.

Sorry, i didn't mean any personal offence.
But experience tought me that development forums looking for the "best" solution end up dead or running in circels, so i prefere not redisscussing points that have been decided for now.


As far as i understand the Xilinx documentation, we are free to connect all I/O pins not needed (almost all in our case exept for JTAG,I2C and Spi) either to Ground or VCC (2.5V).
Leaving them unconnected would increase the chance of noise.

Can anybody please verify the facts about the FPGA pinout. (i am still not so confident i undestood everything correctly)

Fine, I will shut up about the power supply. I understand the importance of keeping the discussion moving, even if I don't agree with every decision.