Topic: Modular FPGA Miner Hardware Design Development - page 27. (Read 119320 times)

For Xilinx, biggest supported Spartan-6 is the XC6SLX75 and 75T (and possibly the equivalent Virtex-6), biggest full-stop is the prohibitively expensive Kintex XC7K160T. I think that Altera's free tools support all Cyclone III/IV FPGAs, and Stratix III support tops out at the EP3SL70.

(Also, my latest attempt to cram a fully-unrolled miner onto the XC6SLX75 just failed place and route. No surprises there...)

Edit: Either I'm hallucinating or this tweaked fully-unrolled miner just completed synthesis for the XC6SLX75. At a uselessly low clock frequency, true, but still...

A little update from m side.

I've wrote to Xilinx and Altera, asking if we could find solutions for the problem concering the payware ISE needed for the Sp6 Lx150 and the altera software.
But ive gotten no response yet. Seems i will have to wait till monday.

Maybe to make this clear.

Wich FPGA's are at maximum supported by the free variants of the software for programming respectivley by Altera and Ximlinx so which would be our fall back solutions ?     Just in case

Most FPGAs are fairly flexible about what signalling voltages you can set them up for, from what I've seen.

Edit: Also, I'm pretty sure the ones we're likely to want to use are meant to be OK with in-spec voltages on their I/O pins whilst powered down.

Actually, as we want to keep the bus open for different FPGAs, we probably cannot specify a signalling voltage that is directly compatible to out FPGA. Instead, we will probably use a different voltage and require all DIMMs to include level shifters to the FPGA voltage. These level shifters would then protect the powered-down DIMMs, because only their FPGA-facing supply voltage is missing. Their bus-facing supply voltage would still be supplied by the bus, so they would be fine. It is a good point, though: we need to carefully read the datasheet of any IC we put on the DIMMs.

I meant a USB interface pin connected to the power supplies remote enable pin, not to the FPGA reset pin. My argument was that 110mW (plus power supply losses!) are too much to justify using the reset state as a sleep mode alternative.

I haven't looked at the specs, but don't most chips require the interface pins to be held below the supply voltage? I am concerned that if you bring down one board, you may bring down all the boards using the same back-plane. Using the USB interface as a buffer should work though.

I would expect that can be done via JTAG as well.

Go one better: reset the complete device and do not load a new bitpattern. This will keep at least the Xilinx devices at their lowest power consumption short of disabling the power supply. For a XC6SLX150, the quiescent currents you get are given in DS162 (DC and Switching Characteristics): a total of 109mW over 1.2V and 2.5V.

So yes, power supply disabling is one extra pin needed on the USB interface chip, but what can it hurt?

Is that even needed? Wouldn't it be possible to load an FPGA configuration that sets it in a sleep state using almost no power? Nothing connected to anything or in tri-state mode.

Maybe I should be more careful: as individual boards, the complete board can be brought up/down at will. You wouldn't be able to address the power of individual FPGAs on one board, though. And if plugged into a backplane, I would have to think a bit first if one board can be powered down without problems for the rest (mostly a question of how the level shifters behave is half off and of giving each slot an individual enable-power signal).

Not RS232: you need an extra programming adapter then: either the interface chip on the hub node or the actual FPGA need to have firmware uploaded to them to understand RS232. Maybe you could bit-bang a different protocol over the connector, but that can't be very fast or portable (corrections?).


Do you intend I2C as the only means of communication between the cards? Then my point from above is again valid: you need an extra cable / bus to transfer firmware to the FPGAs.


We are outside my area of expertise, so correct me if I am wrong: does I2C allow for multiple paths between a master and any given slave? I would have expected a single path be important (maybe not for the 400kHz variant). If a single path is required, you would need to add I2C switches to each board to do the routing.

I must admit the 2D grid of FPGAs would look aesthetically pleasing. But having to replace a single board in the middle seems to be really tough! Actually, how would you even connect a larger set of boards (say, 5x5)? You would have to connect the boards to rows and then plug together the rows, 5 boards at a time!

A resounding "yes". The individual 12V -> 1.2V etc power supplies we have discussed here all have an enable input: if the host interface chip (to USB or later ethernet) deasserts that signal, the power supplies shut off and then only a very small quiescent current is drawn by them (plus the power for the interface chip, e.g. from USB). This has already been proposed, but noone commented on it before. I take your post as a "pro" vote.

I don't want to kill the project via feature-creep, but if the chips can be individually be brought up via USB, can they be shut-down as well?

Uses I have in mind:

• Stand-by computing power for if the network hash rate drops.
• Running from solar power; with the ability to shed load if the sun goes behind a cloud.
• Replacing resistive heater with expensive elements that happen to generate bitcoin

For the standalone board version, perhaps this form-factor is interesting instead of the DIMM form-factor:


http://www.illuminatolabs.com/IlluminatoXMachina.htm

What I like about that type of design:
 - Ultra-modular - you can start with just one PCB FPGA node - provide power, use RS232 to communicate with PC
 - Minimum software development required for the one-node version. Scale the PoC by using a USB-to-multiple-RS232 hub.
 - Step up to PCB-variants - use 2 PCB variants - one with a Atmel ASIC (Arduino?) providing USB connectivity to PC, and power to FPGA nodes. Use I2C to communicate between hub node and FPGA worker nodes.
 - one Hub node could support as many worker nodes as the I2C and power distribution network allows (current, ohmic resistance of the interconnects)
 - Flat design - FPGAs can be easily fitted with heavy heatsinks since the weight is supported by a flat surface, or PCBs screw mounted to a flat surface. Don't care about temperature sensing with a glued-on heatsink.
 - You could implement support for many hubs on the I2C bus with failover capability

 - Low hardware cost? - minimum amount of components, cheap connectors. Cost probably comparable to the DIMM version.

The cons:
 - The hub node concept may be complicated to implement, but quite scalable and powerful if done correctly.
 - It won't be as elegant as the daughterboard-DIMM concept

Just some food for thought.

Disclaimer: I'm more of a hobbyist than a electronics professional. I'm a software guy.

LX75, actually. That is why I was doing my compiles for that chip

I'm no expert on the hardware design, but there is at least one issue against the LX150: It requires commercial software to synthesize the design. The free web edition only supports Spartan 6 up to LX45, if I recall correctly.

Xilinx seems to package the requisite software with their dev kits, so it is likely that someone here has it and could distribute the generated bitfile. But it is a problem for this open source mentality if I cannot tinker with the device I own.

Another question, is there already an open source implementation that works on the LX150? We know there is one for the Cyclone IV, along with a nicer license policy of the synthesis software.

It seems that in the given price range (i guess its just reasonable to limit this on a prototype) we will have to choose from one of the following.

Xilinx:
 
full Spartan 6 Series             (especially The LX150 wich is reported to have archieved up to 190 Mhash/s)

Plus earlier series                 (wich seem to be incompetetive regarding Mhash/€ efficiency)

ALtera:

The cyclone IV Series below 100k LE's              (more would crack my price limit but may be discussed if it shows superior performance)

Earlier series                                                  (May be used if price is limiting or shows better programming caracteristics)   


I would appreciate such a list of performance and Mhash/€.

Status so far:

I've been talking to TheSeven and he proposed the Spartan 6 LX150.He is familiar with Xilinx software desings and may work on that part.

OrphanedGland proposed the Cylone IV series (and also the Stratix Series.But i see them to be prohibitive regarding the prices)

fpgaminer has published a miner software for the Altera Cyclone IV 115. I contacted him for further disscussion of the subject and currently wait for his reply.


Please give your educated comment

PS:

I have my exams at university coming up.
So from now on i will be only be abled to work on the tread once a day until the begin of august.
I think it will go on as smooth as it did up to now.
Thanks a lot for all your work and ideas 


 

I did a testcompile for a ep3c120c8 and get 86% logic cells , Fmax 83 MHz, i did not check which is the next legal clock that a pll could generate, nor did i turned optimisation on. I think with the last design by fpgaminer i got similar results.

If your  rolled up design really works (the last design by fpgaminer does only work  fully unrolled) you could also try to fill this and that chip full with miners to get a estimate how much  logic elements is needed  and  use this as a scale factor for  smaller and bigger chips. And we could calculate a matrix with the cost per MHash/s ...

I think it's already been shown difficult to route even the Spartan XL150 size, so you're not likely to get much useable speed on smaller ones.

Update on Altera speed: This is with using the default settings, in the "Early Timing Estimate with Synthesis" flow, looking at the Fmax value from the "Slow 1200mV 85C Model":

Device	NUM_CORES	SHA256_SEL	ROLLUP	Logic element usage	Max freq [Mhz]	Rate [Mhash/s]
EP4CE115F23C7	1	0	0	96%	87	87

And I only got Xilinx "Post Place & Route Static Timing" when going for the smallest design on the largest chip I can look at (XC6SLX75, NUM_CORES=1, SHA256_SEL=0, ROLLUP=1) with the goal set to "Area reduction" (strategy 2). Even then the map step fails because of a too dense design. I give here the best clock he can find while having 100k signals unrouted:

Device	NUM_CORES	SHA256_SEL	ROLLUP	Slice LUT usage	Max freq [Mhz]	Rate [Mhash/s]
XC6SLX75-3CSG484	1	0	1	71%	52	26

This data is too fragile to make a decision Xilinx <-> Altera. For example, the Altera chip I tried is a lot more expensive than the Xilinx one (exceeding the specified 200EUR limit, actually).

Experts?