Topic: Modular FPGA Miner Hardware Design Development - page 28. (Read 119276 times)

It is only a four-letter link so you may have missed it, but the code is at https://rapidshare.com/files/1053611031/benchmark.zip. I already found the first bug in the ROLLUP, unfortunately:


The new clock speed for the one configuration I showed previously that fits is now 176MHz, so 88Mhash/s (still Synthesis only). "Implement Design" now running.

I tried benchmarking different FPGAs against each other (simulated only, no hardware in hand). For that I took the current code of OrphanedGland, removed the Altera-specific parts from top.vhd and tried compiling it. The interface to the outside world is just a shift register, nothing that would really be used. While I was at it, I added rolling up of the 128-step long pipeline at least for the first stage: divide the size by two for a cost of half the speed.

My problem is: I must have made a mistake somewhere, as even the code without my rolling modification gives ridiculous fast speeds. Normally I wouldn't complain  , but this seems a bit much! Can someone look at the code and tell me if they find the mistake?

In case I didn't make a mistake or the mistake I made does not invalidate the speeds gotten by the compiler, here my results for Xilinx:

I always used the default settings after starting a fresh project. The one exception: I enabled "-write_timing_constraints" under Synthesize. Then I ran the Synthesize target. The later targets (Map & Route) were not run. If the LUT usage in the table is larger than 100%, the hash rate is, of course, purely academic.

Device	NUM_CORES	SHA256_SEL	ROLLUP	Slice LUT usage	Max freq [Mhz]	Rate [Mhash/s]
XC6SLX45-3CSG324	1	1	1	143%	217	108
XC6SLX45-3CSG324	1	0	1	119%	157	78
XC6SLX75-3CSG484	1	1	0	166%	217	217
XC6SLX75-3CSG484	1	0	0	138%	156	156
XC6SLX75-3CSG484	1	1	1	84%	217	108

Can someone who has the ISE Logic Edition or better do the simulation for the XC6SLX100 and XC6SLX150?

I didn't get anything for Altera: I don't know the software that well and there are errors when trying to estimate the clock frequency (Early Timing Estimate gets negative numbers).

Yeah, I know that .... Just trying to make you aware that there are other considerations for a successful piece of kit (any product) besides the technical solution.

Edit: oops, see that you're already doing this ... butting out now.

Saying that I'd probably be in the market just for the interest aspect. What software is freely available and/or supplied?

The question regarding ethernet speed was asked in a diffent forum post some time ago. i think it was asked if the data transfered was bigger that a bittorrent transfer.

but once again i get speed and data transfer mixed up.

How are you planing to connect the dimm bay board to the computer? EDIT - sorry spoted my own error here as you said it would be by usb.

jonboy

I am (mostly) trying to keep size and cost down. I must admit though, that I am strongly underwhelmed by this Arduino: many people do many things with it, but it seems like the wrong thing for this project. Not trying to start a flame war here...


What I write next is not fully decided, yet. So this is my own thoughts: The local power up (12V -> 1.2V etc.) is controlled by a pin of the USB chip. So as soon the the host computer starts up the chip (detects its presence on the USB bus), it will boot up the local power supplies. To power on the external ATX power supply, I don't think concrete plans have been made. It is possible to have the backplane do this the same way as for the individual FPGA cards (by USB detection). It is also possible to assume a "constant on": the laptop power supplies discussed here do not have an enable input.


Why are you assuming a large data rate? The connection is extremely slow: JTAG can be thought of as the acoustic coupler of the on-PCB data busses: every station understands what they say and it is robust, but not really fast. We don't need more for this project.

If you are referring to me mentioning Ethernet: there are some participants of this board who would love to design an Ethernet capable backplane that has its own host computer included. You basically plug it into power and network and it starts mining! It was decided to postpone this for the second version, though: once the USB connected version works, adding the CPU on the backplane is straightforward: there is no extra work involved by going over another iteration of boards and that way is safer.

I was thinking that the arduino could be used for the spi interface mainly but i will bow to the more electronic people in the group.

At a later stage of the idea i was looking at a card desgined like this

http://img696.imageshack.us/img696/6639/fpga1.jpg

But once again with no design or circuit skill i will bow to the group.

Hot-plugging with the arduino in spi interface mode was an idea for the next card not powered by the motherboard to signal it's need for power and prompt the arduino to power up the 400watt psu. Adding cards wuld only be done with the system turned off.

Ethernet - the motherboard has a 10/100/1000 link. As i thought the data rate of the bitcoin network was low?

Would there be far more data moving over the dimm (usb or what ever chip is chosen) link than the ehternet?

jonboy

Admittedly: that would be slow as hell: there is only one MPSSE, so the I2C needs to be done by bitbanging GPIOs. To read out an EEPOM once per boot, it should be good enough, though.

What do you need an Arduino for? The FT2232 does I2C. Edit: Or whatever other USB-chip we decide upon. And I2C has not even been firmly included, yet AFAIK.

The 100mil post system is much worse that the DIMM to hold vertical cards. Only if you have the card parallel to the backplane and use a connector on each end of the elongated board will it be sufficiently stable (my opinion, but plug in a largish card on a few pins and then move it to get a feel).

The text for the pushbutton sounds like hot-plugging. I don't think we want to to there in the first revision: get it wrong and you have fried one or more cards. As for card detection: no mechanics needed: just short two pins in the connector on the FPGA card and the backplane can detect the presence of this connection. And you mentioned the Arduino again. If the backplane becomes "intelligent" in a later revision, I think a bit more powerful CPU would be in order to also handle Ethernet. Or use an even smaller MCU or even a CPLD if all you want is a bit of control logic...

Hi

Please check out http://forum.bitcoin.org/index.php?topic=23015 if you need any ideas on the computer interface side of your project.

At the bottom of the message is my take on a FPGA card. Please could anyone guild me as to what i may be missing on it?

thanks

jonboy

Therefor I would choose next step to be the determination of the FPGA used on the prototype :

- It should be abled to either house the Altera FPGA miner by "fpgaminer" or an optimised Xlinix port.

- Should be in a pricerange for less than 200 Euro.

I'd aprechiate a detailed disscusion of this as it is THE KEY to a satisfying performance

So are we going for Cyclone IV or Spartan 6?
And are those 5A on 1.2V realistic? I remember reading that the S6 pulls almost twice as much, and some headroom can't hurt either.

Okay lets get back to the point:
No offence to anyone but i like to finalise most design features soon.This numbers may be increased with an sucessor to this project.

You certainly got a point there.
I didn't account for the soldering work.
Your caculation might be more realistic for a prototype but has to be discussed at the very end of  the development process.

I am not sure if the 25EUR for the board is feasible. You cannot go with the very cheap manufacturers because of the size constrains for holes, wire thickness, clearances, ... And if you plan to have the manufacturer populate the board, I would guess a factor of 10 in price for the boards, so a total of roundabout 740EUR for the prototype. Later it gets much cheaper for quantities.

I have been emailed by people asking me if we could provide a working prototyp within the next
few weeks and they want to invest multiple thousand Euros into a working system.


So how soon is determined by how long the real routing and developing of a bus system will take.

The how much question may already determined roughly.

If we follow my suggestion above a DIMM populated with 1 Altera 80K Cyclone IV FPGA would be ~155 Euro for the FPGA  ~50 euro for the power supply ~25 euro for the DIMM board
~30 for The motherboard PCB  ~40 Euro for other components (EEPROM,DIMM-sockets,Power connectors,Bus chips)
In addition you would need a ATX power supply and a Pc controlling the boards.
So we might end up somewehre around 300 Euro for a working prototype.

I want to point out that this is just a guesstimation
The demanding thing is to finish and prove a prototype.

Someone has to draw the thing first! I will put my current (1FPGA) board up soonish for someone to convert to the desired board.

How much? and how soon?

Price and availability? ... 

I then would like to state that for the current design we are going to use 2 FPGA's per DIMM PCB at maximum, not more !
In addition the motherboard will hold up to 5 DIMM boards

This number may be increased with an sucessor to this project.I perfer building a small design soon instead of a full size rack solution with 16+ slots we might not pay for at the moment
 

So for two Fpga's this would be ~2.5 A at 12 V max per DIMM

Using all 5 DIMM slots would result in 12.5 A wich should be bearable

The molex connector will be needed if we later want to use FPGA's with higher power draw wich may not be supplied through the DIMM sockets.

That may look something like this (again: clockclick for full size):