As the Wasp Project team moves closer to the working prototype we thought we would post up some details here of the 4 chip A1 Wasp currently in the works. Our modular design will be able to use any ASIC chip that is sold to the community past, present, and future. We will be using Avalon Generation 1 and BitFury chips (even a KnC chip) to test the Hive and Wasp capabilities and as soon as the A1 Bitmine Chips ship December or when the Minion Black Arrows ship in February we will have the ability to fabricate Wasps based on those chips in a very short turnaround time.
The Wasp Project is an open membership collective and we are committed to Open Source Hardware and Software and we are very interested in working with chip fabricators, diy'ers / hobbyists as well as miners looking to upgrade their "ageing" and "inefficient" systems. If you want to learn more or even become a member of the team please check out our Project thread. We should be testing the Avalon and BitFury Wasp (and potentially a KnC Wasp) prototype with the Hive in November and we will post more details in our Project thread here:
https://bitcointalksearch.org/topic/the-wasp-28nm-asic-miner-open-hardware-development-project-299255 This is exciting since there is the potential, for the community especially those with BitFury and Avalon Gen I chips, to buy or build these units in a few weeks time given the prototypes work out well. We are hoping that our modular system will allow our community to develop a variety of Wasps as new chips become available and up-cycle your mining rigs using the Hive modular design.
Quad or Hex A1 Wasp System ArchitectureIntroductionOur Quad A1 Wasp is comprised by five main sub-systems: the A1 hashing chips and their SPI interfaces, the USB interface, the firmware-controllable power supplies, the power distribution circuitry, and the debug, monitoring, and display subsystem.
The Bitminer A1 hashing ASIC is the workhorse of the blade, with 32 fast hashing engines and an SPI based interface for controlling them. Each chip has its own chip select on the SPI bus mastered by the xmega microcontroller.
Control of the entire blade is performed over the USB bus, which is managed by an Atmel ATXmega256A3U microcontroller. The USB connection is a client of the system's main computer/controller, where the mining software runs and connects to the Internet for pools.
Firmware on the microcontroller configures the buck power supplies to provide individually tailored voltages for each A1. The buck controllers also provide many safety features to protect the A1s during hot-plug or power supply failure.
Backplane voltages required by the Wasp's circuits other than the hasher internal power are all provided either directly from the backplane or through the use of LDO linear regulators. This Wasp must provide the VIO for the hashers and regulators, voltage references for the the A/D circuits monitoring on-board voltages, power for the LED indicators, and power to the connectors for diagnostics and monitoring (the optional local console & display). Almost all the ancillary voltage sources are switched and controlled by the xmega, to provide protection for hot-plug circumstances.
Finally, the monitoring and display subsystem is tasked with monitoring temperatures on the board and the power circuits, monitoring voltages, and displaying their various status levels through single- or multi-color LEDs, which can be pulse-width modulated by the xmega.
Voltages and temperatures on this Wasp are monitored through the xmega's A/D subsystem, and through TWI bussed thermometer circuits, as well as through individual sensors in the ASICs and the buck controllers. Provision has been made to attach additional daisy-chained TWI thermometers for the cooling system to on-blade headers. There are several LEDs on the Wasp's edge furthest from the edge connector, used to provide visual identification, board health, operational modes (hashing, debugging, programming, unplugging), and two push-buttons associated with unplugging and manual mode switching. Finally, as mentioned previously, there is a header for the attachment of an external diagnostic and maintenance console, and a firmware debugging and programming header can also be populated.
A1 Hashing ASICsThe bitminer A1 hashing ASICs have 32 on-chip hashing engines for mining SHA256 based eCoins. These engines can run at somewhere between 0.5 and 0.95V, and the higher the voltage, the higher the internal clock can be configured. The chips are nominally rated at 25GH/s each, at 0.65V, and up to 40GH/s each at 0.75V, if all 32 engines are functional. The seller guarantees only that at least 30 engines are functional, but makes no guarantees about any clock speeds or voltage survival beyond the baseline. Our implementation of the voltage controls and the clock controls performed by the microcontroller allow us to automatically characterize and then optimize the running environment for each chip individually, under firmware control. Since the controls can be changed using the communications protocols, a user can also re-configure his blade while it is hashing, in order to lower the power consumed while increasing the ratio of hashes to Watts. The firmware will also, if configured, manage the power and clock to protect the A1 from overheats caused by cooling failures, for instance.
All communication between the microcontroller and the hashing chips is conveyed over the SPI bus. While the A1 has pads to allow the SPI loop to contain more than a single ASIC, there is no benefit to that feature for us, and it involves significant costs in PCB routing - potentially even forcing a change to a four-layer board. Instead, we buffer the SPI bus to each A1, and simply assign a separate SPI select line to each. This allows us the firmware simplicity of talking to a single hasher at a time, and works better than slaving all the hashers to the slowest one's SPI clock or polling interval. It also prevents long shift chains that can tie up the polling system and lower the utilization of the hashers, because one that finishes while others are being re-initialized, must wait up to several hundred microseconds for its new job. It's also cleaner - we don't know what errata are involved in these new chips, and so treating each one independently gives us the best chance at having a fully functional blade, without very costly hot-air rework to replace a poorly performing chip.
The Atmel xmega series contains a USART which can be used as an SPI bus master with DMA, relieving the microcontroller of the duties of servicing the SPI inputs and outputs. This - along with a similar DMA capability on the USB port - makes the microcontroller very responsive to new commands from the mining software and enabling separate work queues for each A1, which are all moving at different speeds, potentially. We don't have to run at the lowest common denominator, and hence can get more hashing out of any given blade than a design that is limited in that fashion.
USB InterfaceThe particular xmega microcontroller selected for this design has an on-board native USB interface whose outputs require only external anti-static protection and noise filters to implement a USB 2.0 Full Speed (12Mb/s) interface. This interface is configured with two device descriptors, making the blade a compound USB device. One device is basically only used for normal mining specification of hashing jobs, and for returning any golden nonces that have been discovered. This makes the miner software simple, and allows it to conform to a single protocol without regard to the type of hashing chip that the Wasp uses. The descriptors also allow for self-identification, as required by the USB specifications, and can show the mining software what opaque configuration data block it might load, to initialize normal operation.
The second of the compound devices is a more complex management interface. It functions to enable FLASH programming, as well as overlay loading and invocation, and can duplicate the monitoring and maintenance reporting for voltages, temperatures, and power supply availability, etc. from the first device. Firmware licensing verification operations are performed using this interface, and it also provides an interface for running diagnostics that can override the first device's commands - or disable them completely.
Power Generation and ControlThis model of Wasp, like every model, uses PMBUS-configurable buck power supplies to provide the variations of main internal operational power to the hashing chips. The IMVP-7 specification has resulted in many viable alternative buck controllers, since they are used primarily in the production of CPU point-of-load regulators, both for laptop PCs and desktop PCs where the graphics processor is implemented on the CPU chip. Because most graphics engines take the same low voltages as the processors, at nearly the same high current levels, there exist dual buck controllers such as the TPS59650 which can create two independent power supplies of the same voltage range, individually programmable throughout the range (0.1-2.5V, in 50mV steps!), at 40A current levels with very low ripple, and monitoring/recovery circuits for over-current, over-voltage, under-current, under-voltage, and synchronized soft startup - all for about $3/per chip, in medium quantities!
Quad A1 Wasp derives all its power needs from the edge connector(s) on its PCB. All backplane configurations provide the following voltages:
This provides drive power for the buck controllers, which generate programmable voltages in the 0.1V-2.5V range at currents around 30A for each section. It, too, is switchable by the Xmega, to support hot-plug. Higher amperage (60A) supply is possible with a second, optional power-only edge connector.
+5Vsb is used to supply all the power to the microcontroller, through a 3.3V low-dropout linear regulator. It is always on, unless the backplane power is completely unplugged, and provides constant availability for the USB connection. +3.3V is used to power the buck controllers, any level translators, and most LED drivers. +5V is the standard switched power that is used only for needs greater than the standby power can supply. It is currently unused on the Quad A1 Wasp. +12V is the main power source for the hashing chips, once it has been conditioned by the buck controllers. With four A1 chips running at turbo speeds, this rail will need to supply the blade with about 160-175W, or somewhere around 18-20A. Other proposed Wasps may use more power, and require the addition of a second power stage connector on the motherboard, bringing the total available power for +12V to 60A.
Power needs for the Quad A1 Wasp involve a few additional voltages derived from the backplane supplies. Low current needs are met with low-dropout linear regulators, while the high current, variable voltage needs of the hashers are met with switching buck regulators, one per A1 chip.
This type of buck controller is perfect for driving a pair of A1's, and the PMBUS is a well known specification for controlling them, which even has pre-built firmware libraries available from Atmel to serve as the basis of firmware development on the Wasp. The Quad A1 Wasp would have two copies of the circuit in Figure-1, below, which would share the xmega between them:
A1 Wasp Power Template
Figure 1: Template for Internal power generation and control for 2 A1's
The dual buck power supply circuit would be a slight simplification of the Texas Instruments reference design available from the manufacturer at TPS59650 Reference Design.
