| Design | MH/s | Device | Process node, $\lambda$ | Area | η (H*pm/s) |
| KnCMiner | 100.0GH/s | Custom
July 22, 2013, 02:59:56 AM
I've been thinking a bit about a process-invariant metric of power efficiency. This is harder because it's so easy to game the power efficiency by playing with the supply voltage -- as it decreases you get a quadratic improvement in joules/op, so in theory the measurement ought to be (ops/(sec*joules2)), but even that isn't going to be constant across all operating voltages -- there are a lot of second order effects. Why not graph it along a set range and then use the area of that graph as the metric.On top of all this, some designs have vastly larger ranges of operating voltage than others. Some chips only work across a narrow band of voltages, others will keep working right up to the point you fry them (my last 90nm chip did this) and all the way down to the point where the chip is consuming less than half the overall system power. Hmm, yeah. So I'm starting to think that any sort of sensible measure of power efficiency is going to have to be a graph. A good first try might be a plot of eta-factor versus joules/op across all voltages in 25C ambient temperature. July 22, 2013, 01:26:06 AM
Od the package, there is also a die rectangle shown - 43 x 43mm, quad core (multi-chip package). Then each die is 21 x 21mm. I doubt that is the die size on the package diagram. For comparison, the Tahiti version of the AMD GPUs which was one of the largest ever chips ever had 4.31 billion transistors. Tahiti was only 398mm2 in size. If you are saying the package has 4 x 441 mm2 dies on it, then it would have a heat density higher than a nuclear reactor. I doubt such a thing could be engineered, but if it was, it would have a hash rate far in excess of KNC's claims. July 22, 2013, 12:04:41 AM
I've been thinking a bit about a process-invariant metric of power efficiency. This is harder because it's so easy to game the power efficiency by playing with the supply voltage -- as it decreases you get a quadratic improvement in joules/op, so in theory the measurement ought to be (ops/(sec*joules2)), but even that isn't going to be constant across all operating voltages -- there are a lot of second order effects.
On top of all this, some designs have vastly larger ranges of operating voltage than others. Some chips only work across a narrow band of voltages, others will keep working right up to the point you fry them (my last 90nm chip did this) and all the way down to the point where the chip is consuming less than half the overall system power. So I'm starting to think that any sort of sensible measure of power efficiency is going to have to be a graph. A good first try might be a plot of eta-factor versus joules/op across all voltages in 25C ambient temperature. July 21, 2013, 05:25:08 PM
EldenTyrell, on the website Bitfurystrikesback.com Mr. Bitfury claims a hash rate of 2.7 GH/s per chip. In this thread, you claim 2.0 GH/s per chip. Please explain and/or correct this discrepancy. That website didn't exist the last time I updated the table. If you click the "2GH/s" link you'll get the most recent posting by him at the time I added him to the table; it shows 2GH/s at nominal vdd and 2.26 when overvolted. 2GH/s is also the figure he gave me via private email. I will be happy to update the entry if he confirms 2.7GH/s/chip; please just send me the link. I'm a bit leery of switching to information from his distributors (who probably don't even have the chips yet!) FWIW I'm still a bit mystified by the photos on his vendors' site showing a QFN chip with "5 GH/s" silkscreened onto it. July 21, 2013, 05:23:48 PM
Data for many old and new CPUs, author colected most data we need here (die size, process node, benchmarks). I agree. That would show another large gap (CPU-GPU) in addition to the GPU-to-FPGA and FPGA-to-VLSI gaps. Illuminating these sorts of generational gaps is one of the goals of the eta-factor. July 21, 2013, 05:23:26 PM
It seems the current formula attaches too much importance to the process node (the path width). I think it should be counted with power of 2 not 3. No, it shouldn't… please re-read the original posting. The feature size is counted to a power of 3 to account for reduction in area (factor of two) and the decrease in gate delay due to decreased channel length (an additional factor of one). Please provide some sort of justification, other than: (The path height is not directly proportional to its width - I think it can even be comparable between the processes in range 28-130 nm. I've found no exact info. I someone knows more, let us know.) What the heck is the "path height"? Are you talking about the channel oxide thickness? That decreases too. Either way, since silicon is dirt cheap the goal here is not to estimate the cost of the physical silicon required as a bulk material -- nobody cares about that. July 21, 2013, 05:20:49 PM
Can we try to figure out this metric for the Block Erupter chips? I can't find the die area Unfortunately we absolutely need the die area… there's no way around that. July 21, 2013, 05:20:42 PM
Not to add to the table yet, until the chip is working. Thanks RHA, I appreciate you collecting this data and putting it in table form. Please let me know when the vendor confirms these numbers (hopefully in something other than a video…) and gives a ship date so we have know when we can reasonably expect third-party verification. KnC's chips don't stand well here. They just took some fpga desing, converted it to asic with some manufacturer's standard technique, and are going to put as many cores on a die as they can. I can't comment on KnC's specific case, but this sort of situation is exactly what the eta-factor is designed to detect -- crappy designs which have simply had gobs of money thrown at them in the form of super-expensive masksets. Products like that do not have much of a future, but you can fool investors with them for a while... July 21, 2013, 05:20:15 PM
I apologize for not responding over the last few days; catching up now….
July 20, 2013, 05:00:53 PM
Od the package, there is also a die rectangle shown - 43 x 43mm, quad core (multi-chip package). Then each die is 21 x 21mm.
July 20, 2013, 04:50:34 PM
We've got info on KNC's die size and the like, how about an update to the OP? That has the package size, not the die size. Or if it does, I did not see it. Jump to:
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