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Topic: Process-invariant hardware metric: hash-meters per second (η-factor) - page 4. (Read 25036 times)

kano

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Quote from: Bicknellski on July 03, 2013, 11:02:52 PM

...
Clearly this a metric in progress and there is probably more that can be done to define it so it can shed light on different designs. Seeking out more information and being academically honest about it is what we need. It be nice for once to come to thread like this one and have people drop the puffery for BFL or AVALON chips etc and take an honest appraisal of the tech.
...

Clearly the progress is zero.

Again, compare the functionality, design and performance of the two chips in questions and you see the metric is pointless.

I guess we could even take it a step further and look at the implementations of 2 certain chips and see it's even worse ... but that's off topic.

The metric is basically ... "If we could actually get the manufacturers to produce chips at the nm size they should have and also parallelised them how many time they should have then here is a magic multiplier (that will get the answer wrong) to say how they compare"
Again the number is pointless and meaningless.

We even have someone ranting about the number of devices delivered so far ... well ... there have been WAY more BFL devices delivered than AVALON devices ... but that is again off topic.

Nothing has really changed since my first comments about the metric and the results even prove that.

kano

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Quote from: k9quaint on July 03, 2013, 10:53:53 AM

Quote from: kano on July 02, 2013, 03:09:47 AM

So ... I come back again and find ...

The Avalon chip that hashes slower than the chip used in the old BFL FPGA, and uses at least 1.5 times the power of a BFL SC (per MH/s) and requires ~15 times the number of chips compared to a BFL SC (per MH/s) and a box somewhere between 5 and 10 times of a BFL SC Single ... rates:

Code:

Avalon	275 MH/s	Custom	110nm, 55nm		16.13mm2	2,836.52
BFL SC	4.0GH/s		Custom	65nm, 32.5nm		56.25mm2	2,441.11

The Avalon above the BFL SC Tongue

Not only that, but the BFL SC is pure custom ASIC, whereas the Avalon seems more and more each day to be a quick a dirty hack implementation.

Again these numbers are irrelevant to anyone but someone who wants to name a new number and pretend it's important.

Too bad you can't read, otherwise you would understand the metric being used.
Or can't you see the screen with your head up Josh's... Grin

All I see if you trying to make an excuse to pick some useless number to say the crappy tiny ASIC chips are good when in fact they suck.
The metric is useless except it seems to apparently show the low tech chips pretending to look better than the low tech crap they are.

k9quaint

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Quote from: Anenome5 on July 03, 2013, 08:42:44 PM

Maybe it's just me, but when you tell me Bitfury has a 2800 score and KNC a score of 90, that really seems odd. Especially considering KNC's gigahash/watt is better than Bitfury's or BFL's. It really makes me question the relevance of this metric to me. Are you saying KNC, or someone, if they had access to KNC's design could replace it with a design that's 30 times more efficient? Are we saying KNC's design is basically one giant fuckup? Doesn't seem to make sense or accord with known facts.

Area is taken into account in this metric. In theory, a gigantic die size could cram tonnes of hash power on a single "chip" and thus compare favorably with Avalon when measured per chip. When you measure using area, it normalizes for this and gives you a "better idea" about efficiency. I am not sure I am a fan yet, but it is an interesting way to measure ASICs Wink

Quote from: Anenome5 on July 03, 2013, 08:42:44 PM

I'm gonna assume that we simply just don't have enough technical details to make a determination and that's why KNC still hasn't been added to the OP list.

That makes more sense.

Syke

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Quote from: Anenome5 on July 03, 2013, 08:42:44 PM

KNC's chip is purely theoretical.

Anenome5

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RHA

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Quote from: Anenome5 on July 02, 2013, 10:13:01 PM

Quote from: runeks on June 29, 2013, 10:11:57 AM

Quote from: ujka on June 28, 2013, 08:47:34 AM

KnC's chips don't stand well here. They just took some fpga desing, converted it to asic with some manufacturer's standard technique, and are going to put as many cores on a die as they can.

So you gather it's a structured ASIC?

Yes, they themselves state it as such.

No, they specifically said it's not a structured ASIC.

Right. I was wrong.
Marcus from KnC said: "this specific design is standard cell ASIC 28nm" (https://bitcointalksearch.org/topic/m.2468045)

k9quaint

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Do you have enough info to do KNCMiner yet?

Anenome5

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Quote from: runeks on June 29, 2013, 10:11:57 AM

Quote from: ujka on June 28, 2013, 08:47:34 AM

KnC's chips don't stand well here. They just took some fpga desing, converted it to asic with some manufacturer's standard technique, and are going to put as many cores on a die as they can.

So you gather it's a structured ASIC?

Yes, they themselves state it as such.

No, they specifically said it's not a structured ASIC.

RHA

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Quote from: kano on July 02, 2013, 03:09:47 AM

Code:

Avalon	275 MH/s	Custom	110nm, 55nm		16.13mm2	2,836.52
BFL SC	4.0GH/s		Custom	65nm, 32.5nm		56.25mm2	2,441.11

The Avalon above the BFL SC Tongue

Not only that, but the BFL SC is pure custom ASIC, whereas the Avalon seems more and more each day to be a quick a dirty hack implementation.

Kano, remember the BFL chips are artificially limited to 4 GH/s because of problems with power and heat density. In different circumstances (bigger boards, one good heatsink per chip) they possibly could reach 10 GH/s or more.
I think we will see such results when people start DIY with BFL chips. There can be of course problems with clock/capacitances/etc. in higher frequencies but the η metric will be quite higher than for current revision of Avalon chips.

As to figuring out η for Block Erupter chips:
(0.336 GH/s / 21.7 mm[su]2[/su]) * (130 nm / 2)[su]3[/su] = 4252.25

It seems the current formula attaches too much importance to the process node (the path width). I think it should be counted with power of 2 not 3.
(The path height is not directly proportional to its width - I think it can even be comparable between the processes in range 28-130 nm. I've found no exact info. I someone knows more, let us know.)
Relevant η' values would be:

Code:

Design           MH/s      Device  Process node,$\lambda$   Area      η'(pH/s)
Bitfury ASIC     2.0 GH/s  Custom           55nm, 27.5nm    14.44mm2  104.74
BFL SC           4.0 GH/s  Custom           65nm, 32.5nm    56.25mm2   75.11
Block Erupter    336 MH/s  Custom          130nm, 65.0nm    21.7 mm2   65.42
Avalon           275 MH/s  Custom          110nm, 55.0nm    16.13mm2   51.57
KnCMiner         100 GH/s  Custom           28nm, 14.0nm  3025.0 mm2    6.48
Bitfury FPGA     300 MH/s  Spartan-6        45nm, 22.5nm   120.0 mm2    1.27
Tricone          255 MH/s  Spartan-6        45nm, 22.5nm   120.0 mm2    1.08
BFL_MiniRigCard 1388 MH/s  2xAltera Aria II 40nm, 20.0nm   306.25mm2    0.91
Ztex             210 MH/s  Spartan-6        45nm, 22.5nm   120.0 mm2    0.88
ATI 5870         393 MH/s  Evergreen        40nm, 20.0nm   334.0 mm2    0.47

The above values are more consistent with the technologies used.

runeks

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Can we try to figure out this metric for the Block Erupter chips? I can't find the die area, but here are the other figures:

Quote from: friedcat on August 09, 2012, 03:17:17 AM

Our chips
Generation 1: Block Eruptor. 130nm with 6-8J/GH. Each chip's rated frequency is 336MHz at 1.05V. It translates to 336MH/s because it does one hash per cycle. The chips work stable and well at 392MH/s at 1.15V. Further overclocking needs proper handling of heat and power supply.

Judging by these pictures, it looks really small:

Quote from: friedcat on December 27, 2012, 09:13:43 PM

Update

After a long and anxious waiting, we have finally got our packaged chip samples at hand. Everyone would be busy in the following 2-3 weeks.

The following pics are taken from my cellphone.

30GHash/s of computing power on one table:

Top and bottom side of the chips:

A closer look at our baby:

These are some numbers derived from the RTL design.

Quote from: friedcat on August 02, 2012, 05:39:17 AM

Update

After further optimization and some trade-offs, we came up with this updated estimation results based on our improved design.

Hashrate: 1.00GH/s per chip
Area: 21.7mm^2 per chip
Power Consumption: 8.23W

Again remember that they are estimated from the RTL design and might have some differences to real products.

We know that the chips ended up hashing at around a third of that (336 MH/s), but the power estimate seems accurate (6-8 J/GH).

ujka

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Quote from: RHA on June 29, 2013, 04:41:42 PM

BTW: Optimizing it to get a chip capable of 3 TH/s is of no use, because it would need to take and dissipate 6000-7000 W of power.

Thanks. Forgot about power and heat. I just reversed the formula...

RHA

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Quote from: runeks on June 29, 2013, 10:11:57 AM

Quote from: ujka on June 28, 2013, 08:47:34 AM

KnC's chips don't stand well here. They just took some fpga desing, converted it to asic with some manufacturer's standard technique, and are going to put as many cores on a die as they can.

So you gather it's a structured ASIC?

EDIT: ~~Yes, they themselves state it as such.~~ No, Marcus from KnC said: "this specific design is standard cell ASIC 28nm" (https://bitcointalksearch.org/topic/m.2468045)

BTW: Optimizing it to get a chip capable of 3 TH/s is of no use, because it would need to take and dissipate 6000-7000 W of power.

runeks

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Quote from: ujka on June 28, 2013, 08:47:34 AM

KnC's chips don't stand well here. They just took some fpga desing, converted it to asic with some manufacturer's standard technique, and are going to put as many cores on a die as they can.

So you gather it's a structured ASIC?

ujka

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If I understand this metric correctly, it gives us some measure of how much design/development team optimized the performance onto the given die size.
I see the best use of it when comparing ASIC technology chips, since they are 'application specific' chips for bitcoin mining (GPU developers had different goals when designing their products).
KnC's chips don't stand well here. They just took some fpga desing, converted it to asic with some manufacturer's standard technique, and are going to put as many cores on a die as they can.
If they did the optimization in a range as Bitfury, Avalon or BFL, they would have a chip capable of 3,000 Ghash.

Anenome5

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Quote from: eldentyrell on June 22, 2013, 01:40:27 AM

(21-Jun) Oh my, this is terribly embarrassing. When calculating the η-factor for bitfury last night I used the gate length instead of the feature size. I have corrected this; please see above. No wonder his numbers came out so high.

Any additional checking of my arithmetic would be welcome.

I was seriously wondering how his numbers were possible!

Okay, now do KNC's numbers!

RHA

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Not to add to the table yet, until the chip is working. The calculated value however explains much.

KnC Promised Figures