This increases the urgency of getting an exact die size for the Spartan-6. We've always known the die size is less than 300mm^2: for one, the package cavity is square but the chip is rectangular: in FPGA editor it's almost twice as tall as it is wide. There's no guarantee that aspect ratio matches the silicon, but it's unlikely to be off by so much that it's square in real life.
I really doubt that BFL is squeezing nearly 2x the eta-factor out of their chips as anybody else, so I now suspect that the Spartan-6 die is substantially smaller than the 300mm^2 package cavity. Unfortunately I seem to have lost the two dead chips I had… argh. I'm almost tempted to sacrifice one of the occasionally-flaky-but-mostly-working ones.
Also keep in mind that there's a substantial amount of per-die overhead for I/O pads and clocking infrastructure, so using two huge chips (like BFL does) instead of five tiny ones (like Bitfury would to get the same hashrate) is inherently a more efficient use of silicon -- but not 2x more efficient. Sadly there aren't any bitstreams for Virtex-class devices that have had as much care put into them as the Bitfury/Tricone/BFL bitstreams for their respective devices.
Edit: the die size estimate for the Spartan-6 was off by 250%; I have actual measurements now (see below).
