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The problem is two fold:
1- AMD soldered the RAM vrm's to pull its power exclusively from the pci-e, without touching the 6 pin.
2- AMD hard soldered two pci-e power lanes to the GPU. So instead of the gpu pulling all its power from the 6 pin, its also pulling from pci-e.
1- AMD soldered the RAM vrm's to pull its power exclusively from the pci-e, without touching the 6 pin.
2- AMD hard soldered two pci-e power lanes to the GPU. So instead of the gpu pulling all its power from the 6 pin, its also pulling from pci-e.
I think you could also add the memory they use is clocked at a high speed and most likely running inefficient, pulling more power. So instead using a wider bus on the interface they speed up the traffic. Fine but then it seems they looked for an additional corner to cut to save costs, its like they said oh lets use 6 pin to save that fraction of a penny in manufacturing and then pull the rest from the mobo.
The electrical engineering guys want to build things right to the proper specs but then you have these assholes that look for corners to cut to increase profit.
