Also all these parties have to communicate and work together:
KnC <-> ORSoC <-> unknown FPGA-ASIC conversion house <-> unknown ASIC vendor
There are so many things which can go wrong when you make an ASIC. Getting it right the first time is hard.
ORSoC
is an ASIC design place, and their upstream provider is a company called eASIC, which I think works with TSMC.
Depends how you define "ASIC design place". ORSoC is more an embedded software, FPGA, and front-end RTL ASIC design house. They are not back-end layout engineers so they will have to get this service elsewhere.
I also thought that eASIC was their vendor, but somebody made a comment and said that they are using a standard cell ASIC, in which they would have to outsource the back-end, layout, place & route work. Which is why I made the figure containing the chain of vendors above.
As I mentioned earlier eASIC devices has FPGA structures (LUT's and routing) and are more similar to FPGA's than ASIC's (cell based), even though they are OTP (one time programmable). However, the turn-around time for eASIC is shorter than cell based ASIC's since you don't have to create all the masks as you do with cell based ASIC's
I agree, ORSoC is only an experienced ASIC front-end design house. There must be a design enablement partner for the 28nm physical implementation.
Besides a structured ASIC service, eASIC has a service called "easycopy". The related design flow looks like a standard cell ASIC flow. So in principle eASIC could be a choice.
But I don't think that they are doing the layout, because it was said at the KnC open day, that the ASIC will be manufactured in Asia.
eASIC has 2 foundry partners: GLOBALFOUNDRIES and Fujitsu.
Fujitsu has no own 28nm fab (45nm is the smallest feature size they produce in their own fabs). So the only foundry left would be GF.
BUT GF has only one 28nm fab, which is located in Europe (fab1 in Dresden, Germany). So if they did not change the foundry after the open day, it's most likely not GF and not eASIC.
Anyway, I think it's better that it is not eASIC, because they just about to start to provide 28nm, there are no proven first time right tape-outs. And the other funny point is, that VMC is claiming to go through eASIC too. Could be a small conflict of interests, if the same team implements two miner ASICs at the same time.
, maybe they get a double summer break next year when their hard work is done! 
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