1. Well sure. Every lie has a great deal of truth. It's the doping of untruth that makes it a lie.
The stage of development you are describing - tweaking FPGA code - is the very *first* stage of ASIC development. This was assumed done ages ago.
And it may have been done ages ago. But when the nextreme 3 wafers (or asics?) came back and proved not working (assuming anything came back), it might have been decided to take the opportunity to tweak the code while waiting for the new spin of nextreme wafers.
If it was done ages ago, and "It uses standard partially processed wafers on which just one layer is changed, and this can be done using an e-Beam; that would be done in house and could be done very fast (within hours literally I believe, but lets call it days)." why did the respin not happen ages ago? This is getting a bit forced.
E-beam process, for those who don't know it, is analogous to handwriting a book vs. printing it using a mask. The expense is analogous. 16GH/sec chips, if 16GH/sec could indeed be produced using this process, would be more expensive than buying competitor's chips retail.
e-beam is more expensive, but the difference isnt quite as large as you suggest for low volume productions. In fact for volumes under 100K, its probably cheaper. Moreover, Im assuming that would only be used for the first lot because it can be done so fast. Once the chip and PCB is validated, a photomask can be made for the top layer(s) and the chips produced in a way thats much more comparable to traditional asics, while still allowing a faster turn around since you are only etching one or two metal layers on to prefabricated wafers. There is still a price penalty compared to a full mask asic, but I would expect those chips to be competitive for quite some time.
Obviously e-beam is very much slower than traditional lithography, see my comment above. You are also making unreasonable assumptions about nextreme 3 which, according to you, is still in development. Do you have any data to substantiate your assumptions?
2. We are not talking about the inherent risks of silicon design, but rather Ken's intentional misrepresentation of the risks taken on by Active Mining.
I will outline these risks:
An illiterate CEO who doesn't know a thing about silicon design and is unable to communicate (you pointed this out, we agree).
A non-contract with eAsic to be a "guinea pig," to use your language.
There is nothing inherently wrong with being a guinea pig. Especially not if you can't see compelling reasons why it would fail. Frankly, Im stunned eASIC still doesnt seem to have nextreme 3 ready. Where you predicting this back in September? If so, I must have missed that.
There is nothing inherently wrong with being a guinea pig if you tell your investors that's what you are doing. If Ken stated that, I would have no problem with it.
If he made it clear that he was an illiterate with no silicon design skills, handing the money over to a company that would use it to fund an experiment, I doubt this Virtual Identity would have been such a raving success. He didn't. Millions were "invested."
My account is about 2 weeks old, which makes it unlikely that I would have been making any predictions back in September. If you wish to entertain hypotheticals, I would point out that had i been in a contractual relationship with eAsic as Ken allegedly was, I would be able to discuss this particular fail with a bit more verve. As it stands, the myriads of red flags were enough for most to call this a scam with 99% certainty. Whether this is a true scam or simply incompetence taken to its pinnacle is an irrelevant technicality.