Topic: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 48. (Read 176727 times)

If You have SPI at 1.2V - 1.8V You can start communicating without shifter.

Connected the SPI bus of the S-HASH board to a (bare)
bitfury test jig. And to make sure things won't get
too hot when things start hashing, all boards were
insulated with Kapton tape and bolted to a heat sink
I found laying around somewhere.



Waiting for some components to come in, then I
can test the level shifters and the SPI link.

As soon I have a bit of time the Avalon S-HASH
board will be redesigned for bitfury ASICs.

intron

(PS: There will be no Rasberry Pi or PC running
cgminer or whatever to keep the hashers busy.
S-HASH has networking and will work stand-alone
if things go as planned.)

Thank you for the explanation! now I get the idea 

You would deserve that $10 million if this works

Thanks for the updates, bitfury. The numbers look very promising, well under your goal of 0.7W/GH/s.

Here's hoping the error rates are also low.

I take it you now will try a few different chips from the sample to see if the results are consistent?

This is REAL sha256 computation. Just no read-back, so there may be high error rate and frequency should be decreased. So there should be no MORE power consumption, question now is only about PERFORMANCE. Also despite what galaxyASIC said seems that I have mastered to design $10 million-worth logic cell library (he claimed that such research costs in range of $10 million USD). If that job is really that complex and chip works, then this technology costs more than $10 million ALONE. But - need to wait of course to check error rates. Without real hashing and reading error rates it can be overestimated and real hash rate can be twice less (clock). Well - and also of course there may be minor bug that ruins whole thing, because development time was very short - that are current questions, not power consumption.

Congrats bitfury, that looks promising!!   

A Hip Hip Hoorray for the most transparently communicating asic dev that I read of on this forum!

Can you roughly estimate how much more power consumation there would be when doing real SHA256 computation?

Cautious optimism giving way to jubilation in 3,2,1...

Raspi driver is about 50 Ohm pmos transistor resistor - with 1kohm you'll get shitty waveform. Just terminate with 50 Ohm and it will work!

Inputs are CMOS, but currents goes in of course when you recharge capacitors. However input levels are sampled using buffer amplifiers (like operational/differential amplifiers), so logic levels may be any you like, just sharp enough edges. Somewhat similar to SSTL... This was built to be able to level-shift using just STRINGS!

You can build devices! GREEN LIGHT! Code that I posted works.

Garbage computation (internal logic misconfigured):
0.596 V 0.541 A 87 Mhz 1 GH/s 0.32 W 0.31 W / GH/s
0.596 V 0.326 A 44 Mhz 0.5 GH/s 0.2 W 0.38 W / GH/s
0.596 V 0.502 A 80 Mhz 0.93 GH/s 0.29 W 0.32 W / Gh/s
0.596 V 0.853 A 155 Mhz 1.8 GH/s 0.5 W 0.282 W / GH/s

Please note that garbage computation consumes LESS POWER than when we compute SHA256 (right now I do not read data FROM chip as have to solder level shifter, but can have conclusions based just on power consumptions. So I can estimate frequency when it falls down:
0.596 V 0.673 A 86 Mhz 1 GH/s 0.4 W 0.4 W / Gh/s
0.596 V 1.049 A 145 Mhz 1.68 Gh/s 0.62 W 0.37 W / Gh/s
0.596 V 1.516 A 235 Mhz 2.73 Gh/s 0.9 W 0.33 W / Gh/s
0.596 V 2 A 320 Mhz 3.72 Gh/s 1.19 W 0.32 W / Gh/s
0.596 V 1.931 A 400 Mhz 4.65 Gh/s 1.15 W 0.24 W / GH/s (please note - HERE WE DO NOT COMPUTE USEFUL HASHES LIKELY!)

Then - voltage sweep (limited to 3 Amps now):
0.65 V 2.56 A 410 Mhz 4.77 Gh/s 1.67 W 0.35 W / Gh/s
0.687 V 2.997 A 467 Mhz 5.43 Gh/s 2.06 W 0.38 W / Gh/s
0.545 V 1.52 A 280 Mhz 3.26 Gh/s 0.83 W 0.25 W / Gh/s
0.5 V 1.07 A 216 Mhz 2.5 Gh/s 0.54 W 0.21 W / Gh/s

Clock is set by using internal SLOW oscillator programmed with code:
{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x0f}; - with code 0x1f not works

But clock likely would be different.

Now I have to test read-back and test real error-rates, as there can be up to 30% and it won't be noticed just with power consumption, however 80% error would. That's it... Very little chances still exists that we fail (as models match with practice is very close, close to measurement limitations of my equipment, I am amazed really), but real life differs from theory (i.e. I wouldn't loose bet if everything would go as expected :-).

By the way board isn't bad at all - with 1 W we had 46 degrees board temperature with 26 degrees in a room... and it lives USB-stick could be nice product with these chips!

? Are there any currents running into your inputs then?
It's a CMOS process, right?

intron

RasPI is too weak for serial 1kOhm resistor. Bitfury took only 50Ohm parallel to Zener. I hope we will be able to post final setup that can also read MISO.

Yes, that's ok. I'm usig now a 1K/1K2 voltage divider
with a zener parallel to the 1K2 resistor. In that way
3V3 signals are 'level shifted' to 1V8 signal levels.

A zener is really needed to fight ESD, did tests with
an ESD gun for many many hours years back. Just hoping
that the on-chip PN-juntions will help you withstand ESD
is begging for trouble. Adding a simple zener and you
can withstand 16kV full contact charge injections, almost
without end. You can forget about the 'two shot 4kV human
body model air discharge' and all that when a zener is present.

intron

thanks guys for the frequent updates, we really appreciate your work here!

regards

Well... We have some progress here..

Images

Efficiency measures will follow shortly.

look very nice
Especially with that chip on it

@Intron

Ultimate test is if You get the correct signal voltage on chip pins. If yes, the setup is ok.
Bitfury connected resistor parallel to zener (not serial) and removed zener :-).

Wow, congrats so far!

Well - that's not exactly voltage divider! As it is formed not with two resistors, but

with internal pmos resistance of raspi driver and external termination 50 Ohm resistor mounted on PCB.

Zeners for ESD... hmm... 2 kV HBM model is a 100 pF resistor charged to 2 kV passing through 1500 Ohm resistor... current can be pretty high - amperes... This is what should be passed by built-in ESD diodes actually well.

Zeners were choosen to provide for ESD protection and
to allow for variable input voltages. The voltage levels
of the control processor where unknown during the design,
could be 3V3, 5V or even 2V7.

Will use a voltage divider also now.

Use zeners as input protection all the time,
never had issues.

intron

Well... First results...

Board seems to be good enough at least for lower-power test! We placed 15 1uF murata capacitors. We placed also 10 uF kemet capacitors where tantalum capacitors were expected and into input vdd we placed 1000 uF electrolytic cap. Connected this to lab power supply. Should be good enough.

Connected power to IOVDD as well. IOREF was tied to VDD (sorry no 0402 resistors at hand).

Before applying power - I've used multimeter and checked all ESD diodes - good way also to check that all connections are in place - on every pin there's path to IOVDD and path to GND - you can check it - say there's diode between GND |>| INCLK and diode between INCLK |>| IOVDD - by checking them you'll know that chip ESD not broken at that all connections are in place.

Then - checked buffer issues... Well with 100 mV hysteresis they're sensitive bitches. So DO NOT APPLY SLOW RISING SIGNALS.

For raspberry pi solution was pretty straightforward - just load output with 50 Ohms and you'll get voltage divided to about 1.8 V, nice sharp edges and no ringing!!!

This is what should be done instead of series resistor and zeners. This likely may be reason why Taiwan test failed.

Its Beautifull! Who else from ASIC companies translate his baby born?