Topic: [ANN] OpenBitASIC : The Open Source Bitcoin ASIC Initiative - page 13. (Read 50782 times)

Very interesting topic.
Watching closely...

It's unfortunate that manufacturers of these high-end FPGA development boards seem to provide limited publicly available amounts of information on their products -- not enough to base a purchasing decision without direct contact.  Neither Gidel nor Polaris provide any information on the power handling capability of their boards.  Without PEG connectors, the Gidel PCIe-based boards are going to be limited to either 25 watts or 75 watts at the slot depending on whether they are configured as a graphics card.  I don't think 25 watts will be enough, although 75 watts may be.

Altera lists a number of manufacturers of development boards on their site at http://www.altera.com/products/devkits/kit-dev_platforms.jsp.  Of the boards there, I like the Polaris board mentioned in a previous posting and another board by S2C which provides more useful information about their offering than other manufacturers:  http://www.s2cinc.com/product/HardWare/S4TAILogicModule_Single.htm  S2C claims that their on-board regulators handle up to 120 watts of power, which already makes them preferable to a PCIe-based board like the one from Gidel.

I will report back when I have more detailed information including pricing on these two boards.

Quartus II software costs $3K to license for 1 year, which should be more than adequate for this project.  Free 30-day demonstration licenses are also available for interested parties.

Compiling (synthesis, placement, and routing) for large FPGAs/ASICs is both CPU and memory intensive.  Quartus has a limited ability to take advantage of multiple cores, so it is actually more beneficial to have a smaller number of faster cores (in my experience).  I have only attempted designs for 1 or 2 full mining cores so far because anything more and I run out of virtual memory on my development machine, but if I were to extrapolate based on the memory usage I have seen, it is roughly 1.25G per mining core synthesized.  I suspect a 16G Linux or Windows 7 machine with at least 48GB of virtual memory could be made to work, though it's quite possible that paging would make the compilation unacceptably slow.  Given that RAM is relatively inexpensive, I'd prefer to see 32GB or more.

Centrally located -- presuming there is more than 1 developer, it should be located somewhere with a high-speed internet connection.  A data center is not necessary, although it could certainly run on a cloud based system and that has the added advantage of allowing easy scaling of the "hardware" in order to adjust to the optimum balance of performance within budgetary limits.

The FPGA development board, and later the Hardcopy prototype board would need to be physically located with one of the developers since the physical configuration would need to be monitored and occasionally changed.  Access to the FPGA/Hardcopy hardware itself by other developers would be provided via a mechanism like logmein/remote desktop/ssh.

Access to the systems should be restricted to the developer(s) on the project.  Occasional WebEx-style meetings could be held with investors using the development systems in order to provide demonstrations/progress reports if desired.

^ post 666!

Don't curse OpenBitASIC

Maybe some for-profit investors would settle for a time advantage: give them access to the design 3 months before it gets opened to the public.

What's important in the end is that everybody can get a piece of the most efficient mining hardware for, say <1k USD. That is the only way to ensure Bitcoin mining does not get monopolized to a point where Bitcoin essentially loses its greatest strength: decentralization.

@SgtSpike: I wouldn't limit the pool of potential investors to miners alone - anybody who doesn't want Bitcoin to fail in the long run should have an interest in Bitcoin mining staying decentralized. This initiative is IMHO a very important step towards that end. I'd definitely help funding the development of such an open ASIC design!

Another boards manufacturer found, and I just asked for pricing :
http://www.gidel.com/PROCBoards.htm

It might work!

Best of luck getting it going however you do it. 

You may be right, but if we go with for-profit only, investors will require a complete closed-source approach. So, I envision a mixed way.
Crowfunding for the initial design and prototyping, all this steps (just before ASIC manufacturing), will remain always public domain.
Crowdfunders (as well as the tech team) will get company shares and some privilege buying in the first production batch .
ASIC production itself, which is the most expensive part, can then be funded by private for-profit investors.

It'll be tough, but I'll choose to be optimistic. 

I think you are vastly overestimating the contributions you will receive from miners before having anything to show for it.  Even if you promise them a unit for 100BTC, finding 500 people willing to pay that much money up front for something they can't guarantee will ever exist is a stretch...

I think more likely, you'd be able to find a group of investors to invest in a for-profit company in order to fund the development of the ASIC.

How much memory do you need, and how much does the software cost? And how do you plan to allow access, and where is "centrally located"?

Also in regards to the machine specs, what are the bottlenecks of the software other than memory? Would a fast processor or storage subsystem help a lot? Fast memory vs slow?

I welcome any other input.  This is a multidisciplinary effort, and could definitely benefit from others individuals with experience in hardware design, HDL programming, ASIC design, to say nothing of the business acumen needed to make it all happen.


Certainly.  I will look into this further in the next day, but right off the top of my head it seems to me that phase I could be considerably shortened by putting off the design of a completed board for the ASIC until later, and using an existing development board with the FPGA predecessor to the Altera Hardcopy device.  The appropriate prototype FPGAs for the HC4E35FF1152 Hardcopy device would be one of the EP4SE230, EP4SE360, EP4SE530, or EP4SE820.  The last device would be preferable because although it costs more, it has 820K LEs on it.  This is still considerably less than the Hardcopy IV device, but it is at least large enough that issues surrounding the operation of multiple miners in parallel could be tested and debugged ahead of the final design.  I'm sure there are several companies that make the necessary boards, but a quick search turned up this one -- http://www.polaris-ds.com/products/boards/tile-board/ -- as one possible candidate.  It looks like I will need to contact sales for a quote, but I doubt it would cost more than $10K, and probably considerably less.

Beyond acquisition of the board, a suitable development machine (with a reasonably fast processor and LOTS of memory) would be needed, and probably the Quartus II software would need to be licensed for it as well.  All of this hardware could be located at a central place with good internet connectivity.  This would allow multiple people to be involved with the development while limiting the initial cost outlay.

With regards to the software, we would benefit in time tremendously from not re-inventing the wheel here.  Fpgaminer has released his code under the GPL, so I believe we are free to start with it as the basis for the design (and this includes Makomk's enhancements to the code).  Some further tuning can be made to the code, but the main thrust of the development should be the development of an architecture which will interface gracefully to an existing mining front end like cgminer.  I suspect that would meet with more approval from the community than developing an entirely separate software front end as others have done, and it certainly should cut back on our development time as well.

Actual time estimates are tricky, so please take these with a grain of salt.  Doing a more accurate estimate would require breaking down the development into smaller pieces, and that is something that should be discussed with all of the developers at once (I'm assuming that I would not be the only developer on the project).  I estimate about 2-3 weeks (depending on the exact feature set decided upon) to modify existing HDL code to enable multiple miners to run in parallel and to operate efficiently over a common communication bus for accepting work packages and delivering results.  I estimate a further 1-2 man weeks of development time to construct an interface (USB, etc.) to interface the miners on the FPGA/ASIC to the mining front-end software (such as cgminer).  Hiring expert consultants to perform the above HDL development could reduce the time estimates by as much as a factor of two, although with significant added cost.

A more ambitious approach may include the ability to run the system as a standalone miner.  An ARM processor or a soft-processor running Linux could be used, and from there it would not be too big of a jump to adapt existing mining software to run directly on the system.  This would increase development time and risk, and may be something best considered as a later add-on (easily doable by making the original design modular).


I think HK is an excellent jurisdiction for such a company due to very advantageous taxation rates compared to other countries as well as the strong rule of law and easy access to China for cheap manufacturing.

By the way, when it comes to the Hardcopy side of things, I came across the following link on the Altera site: http://www.altera.com/devices/asic/hardcopy-asics/about/hrd-development-methodology.html  This is comforting as it shows that relatively small amounts of time are needed to go from a completed Hardcopy design to samples (albeit large amounts of money are required).

The numbers are surprisingly good.  I would have guessed closer to about half that rate before I did the build.  I would be more comfortable having done a full-scale build (with 25-30 miners), but I'm going to need to put together a considerably beefier development machine to do that.


I ran the Powerplay Power Analyzer on a single instance of the design (and I had to put it into a smaller Hardcopy device, since it was not supported on the largest device I originally used).  Using a 50% average toggle rate, the power was estimated at 1.2 watts.  Multiply this by 25-30 miners which could be fit on the device, and you have an estimated power consumption of 30-36 watts.  I suspect that Butterfly Labs may have done something similar when they came up with their original numbers for power consumption which proved to be way low.  However, even with a toggle rate of 100%, the estimated power consumption would come out to double the above which is 60-72 watts -- still very reasonable.  I would consider these numbers very preliminary as well.  Another data point is that Altera claims a 50% power reduction over an equivalent FPGA design.

Power consumption is a very important part of the design since it could prove to be the limiting factor for performance so you are right to be concerned about this.  In terms of MH/J, however, it should be head & shoulders above everything else out there now, even at the 40nm level of the Hardcopy IV device.

Excellent data you bring to us, Jason. Given the high expectations for ASIC's mining to be made, I think 200-250k funding is absolutely possible, we are only talking of 500 miners willing to fund 100 btc each.

Unless any other tech expert comes with a better proposal, let's analyze the Altera Hardcopy path with some depth.
According to previous post, the first step will be :

"Produce PC board with predecessor FPGA on it. Develop/test mining software on it to prove design".
Can this step be ellaborated, and estimate material costs and man hours ?

On the legal side, I will register company in Hong Kong (any other jurisdiction proposal ?).
This is $1200-1500 cost, and I can fund this until 1st round of funding is made.

On this matter, all funding will be done thru escrow, for the funds to be 100% safe.
I would much like a multi-sign approach for the funds, but AFAIK this option is not still available.
Also considering of using GLBSE for crowfunding, if they can also make escrow service done, all ideas are welcome. 

There probably is, but just to be safe, multiply the numbers that the compiler spits out by 2 or 3.

Jason,

Thank you so much for finally producing some numbers.

Since the initial announcement of butterfly labs last year Ive been speculating they used HardCopy to achieve their original claims (1GH/s 25W IIRC), because it seemed to make perfect sense.
 Your numbers even far exceed what I would have expected. Even if you take them with a few table spoons of salt, its hard to understand no one seems to have gone down this route yet. Unless BFL actually did, but on a much older, cheaper design and process.

Is there a way to guesstimate power consumption in your simulation?

You don't need to ask the question IF there is interested, based on what has been seen with BFL.  Demand is far outstripping supply with them, not because they are selling an FPGA, but because their FPGA is so much better than anything else out there.

If you (or a crowdfunded management team) makes an ASIC that is along those lines, there WILL be lots of interest for it.

I have been working with the FPGA designs by fpgaminer and ztex for some time now.  For a while, I was interested in seeing what might be possible with the relatively inexpensive Cyclove V which was recently released by Altera (looks like it might edge out the Xilinx LX150, but nothing definitive yet).  But even if it does wind up beating the LX150, it will still fall significantly short of the mark set by Butterfly Labs, so it's hard to become too excited by the idea.

Obviously, a much larger leap is possible going to a full ASIC design, and it sounds like that may already be in the works based on what others here have said.  However, undertaking a full custom ASIC design not only takes a fair bit of cash, but it is also fairly time consuming compared to alternatives.  In the world of bitcoin, things can change very quickly so I can't see investing my money in a project which would have a payoff more than around 6 months out.

That seems to leave Altera Hardcopy on the table.  Like a few others here, I did some basic research into it and it looks like $200K is what it would take to have a die made along with some samples.  Add a bit more cash on top of that for some test designs based on the FPGA equivalent of the Hardcopy device (Stratix), and it seems like something that could almost be crowd-funded.  Maybe in phases:

• Produce PC board with predecessor FPGA on it.  Develop/test mining software on it to prove design.
• Produce Hardcopy version of design with assistance provided by Altera.  Populate test board with sample sASIC and test/verify operation.
• Purchase n sASICs and populate n boards with them.

Each phase would require additional cash, but all three phases should be able to be completed in under 6 months.  I don't know exactly how long phase 2 would take, but I think phases 1 and 3 could take around a month each if carefully managed and some overlap may be possible between the phases as well.

Now on to some performance numbers...

I took a slightly modified version of code originally developed by fpgaminer and subsequently enhanced by makomk.  First, I built it for a Stratix IV device, and then for the corresponding Hardcopy IV device -- the HC4E35FF1152 which has the largest number of H-Cells of any Hardcopy IV device.  Due to memory limitations of my build machine, I was not able to compile more than 2 full miners on the chip (each miner needs about 1.25GB of memory for synthesis, and I haven't yet upgraded my development machine with the needed ~48GB of virtual memory that would be required to compile a fully populated device.  However, some interesting extrapolations can be drawn from what I did do.

First of all, a single miner compiled for the HC4E35FF1152 uses 306,648 H-Cells, with no optimizations enabled.  Fmax is 316 MHz for the slow 85C model.  But wait -- the device has a total of 9,774,880 H-Cells on it.  So you could theoretically fit 31.9 miners it with no optimization.  Assuming it's possible (with optimization) to fit 30 miners on the device, and (with optimization) reach 300 MHz per miner, I get 9 GH/s hash rate.  Perhaps it would be more realistic to go with something like 25 miners on the device, though in that case it should be possible to get a slightly higher Fmax (say 325MHz).  That still gives over 8 GH/s.

I have not tried this with the Stratix V/Hardcopy V devices, though I can only assume that their performance would be higher given the large number of H-Cells available, and the smaller geometry used.  I would expect over 10 GH/s.

I would expect that the boards with an sASIC could be manufactured for around $1500 in reasonable quantities (500+), though this should only be taken as a ballpark figure as I have not yet been in contact with Altera to work out more exact costs of producing the sASICs.  I'm assuming they would cost on the order of $1000 each.  If fully populated/tested hardware were then sold for $2000 each, that would yield a minimum of 4 MH/$, which I think is better than anything else out there at the moment.

Everything I've written above is very preliminary.  I wanted to get a feel for the ballpark level of investment that would be required and the performance potential for a miner based on Altera Hardcopy.  If based on the above very tentative numbers, there is enough interest in pursuing this further, I would certainly be interested in playing a role.  If not, then I'll go back to playing with Cylcone IVs and Vs for the fun of it.

This is a great idea; however, let me set some expectations for the community regarding the cost of producing an ASIC. With ASICs, you have four different choices:

1. Academic "wafer sharing" - this lets you get a very simple design fabricated on a very "old" technology. Wafer sharing doesn't allow for large volume production - it's for research projects. However, wafer sharing is cheap.

2. Structured ASIC - http://en.wikipedia.org/wiki/Structured_ASIC_platform; this lets you relatively easily transition from an FPGA to an ASIC design, using a chip that has the first few layers already populated with an array of standard logic. Essentially, you just provide the wires to connect up the logic in the way you want it. Expect to invest close to $1M to produce the first run of a structured ASIC design.

3. Standard Cell - http://en.wikipedia.org/wiki/Standard_cell; this lets you build your own ASIC by assembling networks of standardized components. All of the layers of the chip are up to you. The cost of a standard cell design using recent processes these days is $5M - $10M.

4. Full Custom - Faggedabahtit; full custom designs achieve the best possible performance, but rely on literally designing the entire chip from the ground up. Companies like Intel use full custom processes to highly optimize their processors for the absolute maximum performance. Cost: $100M and up.

Given these four options, a community designed ASIC is probably best served by the wafer sharing model. However, if enough people can put their heads together to raise $1M or so, a structured design would definitely provide the best ROI. If Bitcoin explodes in popularity and the mining / transaction reward can be measured in $10Ms per month, then standard cell or full custom designs will be funded easily.

Yes, making a design isnt free, but for something as "simple" as a bitcoin asic, thats almost noise compared to the cost of a maskset on a modern process. The actual cost isnt even so much the time of the engineers, its the software (and hardware) they use to produce the design thats ridiculously expensive. Who is going to contribute that?

 Also if you factor in the disadvantages of a softcore, its possibly not even cost effective to use it, even if it was available for free. I could be wrong there, but it wouldnt surprise me.

If you want to do something opensource, I would encourage you to look in to s-asics, particularly hardcopy by altera. Those are essentially hardcoded FPGA's. Compared to regular FPGAs, they appear to offer significant advantages on almost every important metric: die size, power consumption, and performance. Compared to ASICs they offer a much lower NRE.

Alll you need for this to work, is a proper bitstream for Altera FPGAs.  Once you have that, anyone can go to altera with that bitstream and order a batch of 50 or 100k s-asics for a price thats at least more manageable than a true asic. What I dont know is what kind of performance you could eek out of an altera fpga.