Topic: [ANN] OpenBitASIC : The Open Source Bitcoin ASIC Initiative - page 9. (Read 50782 times)

+1

To be clear, when I talk about cost, its mostly NRE. Per chip cost for packaging or sockets is quite low in volume, but thats not the main concern here. If it helps, a few years ago I remember a custom BGA package for a mid sized chip cost us around $40K. LGA is likely considerably more expensive than that, MCMs, I dont even want to know. That stuff was exotic for intel and amd just a few years ago, I dont think its affordable for mere humans yet.

OK, still learning. If it really does cost significantly more, then I suppose it isn't worth it. But what I want to find out is some actual cost estimates - how much more? I was thinking specifically in terms of power density when I was imagining this kind of setup. I guess I always have considered density above cost, just because that's what I do.

MCMs (multi chip modules) like that are not exactly cheap or easy to make. Its not the per chip price, its the NRE.

There is no point for a bitcoin asic, there is no high speed IO or low latency interchip communication. Power delivery aside, you could put dozens of those asics on the simplest cheapest PCB, why make it much more difficult?

Right, so what I was thinking was that there would be one standard size die, small enough to be really cheap and fit on a small package, and then the large package would contain several independent dies. Like this:



^ That is the VIA Quad-core chip, with two of their Nano X2 dual core dies on one BGA package. Now if we assumed that the die size was small, like 10 millimeters square or so, you could squeeze several of them on. They would fit because of the limited number of communications and power lines needed.

depending on node, an ASIC could be 10x to >50x as dense as an FPGA. You could cram plenty of "cores" in it. But you wouldnt want to make the asic as big as possible, you will want to make it as cost efficient as possible. There are lots of trade offs to be made, packaging cost, pcb cost, etc, but in general, smaller die size gives you exponentially higher yields and is therefore preferable.  


See above. Its not the package thats your limit, its the yields that would plummet if you design a monster size asic.  Ive seen reticle size cmos image sensors that yielded two or three functional chips per wafer because they were so friggin huge. Since hashing power scales linearly with the number of chips, there is no reason to make such uber sized chips. Many smaller chips would perform identical and probably end up being a lot cheaper.

Well I wish I even knew the much the stuff actually cost. For instance, even if it isn't LGA as such, AMD's Semprons are less than 50 bucks for the whole thing, including the useless processor inside. And you can buy entire motherboards to fit them for another 50 bucks. I realize the both are getting heavy volume discounts on all the parts, but for a $2k mining chip, it seems appropriate. If it isn't going to cost that much, that is why I was suggesting that multiple cores be placed on such a chip - this would allow the cheap chips to be a single-core, plastic package, and the 1% would have the option of buying $2-5k multi-core chips with double, triple, quadruple the hashing power.

The benefit for people here using a standard socket is that you can use commodity heatsinks or waterblocks which would lower the cost. I'm not sure that would offset the added cost of packaging it in something like a AM2/LGA775/LGA1155 package and buying the socket vs just soldering a BGA right to the board, but something like a Coolermaster Hyper212 would provide a lot more cooling for $20 than anything you'd find to fit a BGA chip.

The best way to have the community invested is by letting as many invest as possible

The reason I suggested it was because I was thinking about packing as much silicon as possible into the size of an LGA package. The more hashers, the more wattage, and I think the existing wattage estimates are for some fairly small dies. If we have 4 of those dies, or even more than that if they are small, it would raise the TDP considerably. Furthermore, it would allow for overclocking headroom. A standard CPU has a fairly small die in a comparatively large package, because of all the communication pins that are needed - but if we only need a few pins, we could perhaps cram a huge die into an existing package type.

LGA packaging would make the boards a lot more expensive and really serve no purpose; first of all, for watercooling etc doesnt matter if you use LGA, BGA, TQFP or anything else, though it might be interesting to make sure the physical dimensions of the mounting holes and thickness match those of a popular CPU socket.

Then again, even that doesnt make all that much sense, an ASIC would likely be so low power, that just a glue on passive heatsink is all you would need.

Oh well, I was kind of hoping we could have a continuous collaborative project going on here, but I guess that doesn't make much business sense.

Have you been able to determine volume pricing for proper metal chip packaging versus plastic? I know Fujitsu has a packaging plant that can handle LGA packaging, like a CPU, and others do too.

I've always wondered whether you could make a standard size ASIC core and then make a product range consisting of chips with 1, 2, 3, or even 4 of those cores, all in the (fairly expensive) LGA packaging. Although it is expensive, I feel that it would be worth it because of the huge amount of aftermarket parts and accessories such as watercooling stuff that is already designed for the LGA form factor. Even the existing CPU sockets are designed to hold chips that have a TDP of upwards of 150 watts! I guess this would be the ASIC for the 1%, but someone needs to make one sometime.

bravo

Quick Update:

We have been in touch with Altera regarding their Hardcopy product.  Given the costs involved are considerably higher than we originally anticipated, we are considering other alternatives before making any commitments.  The alternatives involve ASIC technologies and do not use FPGAs.  Although we don't have final prices for everything yet, the alternatives appear to be competitive with Hardcopy, offering similar performance levels, potentially with lower costs.

Meanwhile, development of the mining system continues.  We will soon be validating the HDL on a large Stratix IV device and once everything is working on it we will have some baseline performance measurements from which we can relatively accurately extrapolate performance of the final devices.  Bitfury's earlier comments on performance levels of Altera devices (Stratix IV and Hardcopy IV) in this thread are more-or-less in agreement with our own estimates.  Regardless of the final hash rate, our goal will be to get as close to the 4 GH/$ mark as we can with our entry-level miner, which is well beyond the current 1.4 GH/$ mark set by existing BFL singles.  It is also well out of reach of the performance levels achievable by miners based on FPGAs that are available now or likely to be available anytime this year.

We are approaching this effort as a business, with the goal of being compensated fairly for our time.  So this will not be an open source community project.  To be sure, we will release our new code, schematics, and other aspects of our design under the GPL.  This will happen only when they are substantially complete.  In any event this will happen ahead of the product being released so that everyone can take a look under the hood before purchase and tell us what horrible engineers we are! 

Jason

Seconded

Sub.
(Forum admins: please install the SMF Bookmark Mod to avoid these noisy "sub" posts.)

waiting if GLBSE funding will be available! Interested thx

Well. I am pushing now hard to make LX150 at price near/below BFL. Talking to many people found that Rack design we built for ourselves and our investors in not that people want. So we started 4U-box design initiative. Although single-boards orders may be supported as well. And meanwhile discussing with FPGA-vendors about prices. I suppose that first batch for 4U devices will be around 500 chips, not less, if good price needed.

https://bitcointalksearch.org/topic/bitfury-design-licensing-mass-production-83332

I'll soon (hopefully today) post mechanical drawings of board there, airflow simulation, protocol proposal, etc. Meanwhile soon I'll meet with Altera guys and discuss future of their chips vs LX150... But that fastest LX150 bitstream actually makes hope that we'll get good prices for Altera for more or less baseline unrolled bitstream like I used in sims here priced competitively... Then there will be quite long iteration to improve Altera's bitstream, which could take about same 6 month... etc... Opensource releases will lag of course closed-source production, as I suppose that crowdfunding like offered here

https://bitcointalksearch.org/topic/m.918125

would not bring money necessary to make all these things work.

So all of these gives me clue that today we'll get "competitive" price at about $0.60 per Mh/s, at the end of year about $0.45 per Mh/s, in mid of 2013 at about $0.30 per Mh/s etc, at about end of 2013 at about $0.15 per Mh/s, and then it finally would land on Moore's law with ASIC things but like cell-asic 45-nm with some custom cells indeed, decreasing with less speed. But - to make these things to happen, overall mining market should grow (i.e. difficulty AND exchange rate of bitcoin), so it would be interesting to throw more resources to developing these things. So I feel with FPGAs in much safer region.

This sounds pretty rad, I am interested to read further and to contribute in being able to support manufacturing.

  @ Bitfury.  Thanks for inputting on this.


A concern comes to mind.  From what I understand you are taking an approach of long-term FPGA volume commitments vs. sASIC?

Are such long term commitments feasible?