Do You plan to support Ztex 1.15x fpga boards for mining? I've got four of them lying down around and could play with them.
Is there only need to bitstream changes or in cgminer sources too?
If bitstream then I think that constraints file changes will not be enough to work ztex 1.15x properly because of CPLD chip absence in 1.15x version.
Could You give me any other hints, i'll give a try. Contraints .ucf file changes should be easy for me, I've done some easy HDL projects so far.
Is there only need to bitstream changes or in cgminer sources too?
If bitstream then I think that constraints file changes will not be enough to work ztex 1.15x properly because of CPLD chip absence in 1.15x version.
Could You give me any other hints, i'll give a try. Contraints .ucf file changes should be easy for me, I've done some easy HDL projects so far.
Its been requested but I've been taking a bit of a break from coding recently (a touch of burnout, not helped by the tendency of the Xilinx ISE to arbitrarily refuse to route stuff).
The bitcoin mining verilog source code and Cypress MCU firmware is a good resource (link), specifically the source package (link).
I think the 1.15x is compatible with the 1.15b code, though looking at the web page it has different hash rates (due to different devices LX150 vs LX75), so I'm not so sure now. EDIT, ah its actually the 1.15d that's compatible with the 1.15x, so scratch what I said about the 1.15b, and the following paragraph is now irrelevant.
IGNORE ... I made a start on a port for my litecoin miner to the 1.15b a good while back (link) but never got as far as testing (I don't have one, and it was really just as a discussion point with another member, vpereira, who's rather dropped out recently), but it may be of interest. Not that the litecoin project is going anywhere, the hash rates were just too low to be useful.
The absence of the CPLD just affects the bitstream upload time, the actual firmware runs on the Cypress EZ-USB chip and it claims to be compatible (link). Cgminer should be fine but you'll need to replace the correct bitstream file. Its a bit confusing as there are d1, d2 and d4 versions. I assume the correct one is selected depending on the version of the board? I'd need to dig through both the verilog and the firmware source code to check this. OK, probably just the d4 variant you want to use (the d1 and d3 seem to just be earlier versions of the code with slightly different interfacing which might confuse cgminer). Actually cgminer was the hardest part of getting the ztex 1.15y port working, so may well be an issue here. Its easiest to build on linux if you need to tweak it, but its doable on windows with a bit of hassle to get the build environment set up properly.
I did a diff between the bitcoin d4 and y1 code, and its just the select logic that's different (and a tweak to pll_stop buffering which seems irrelevant). So assuming d4 is good for the 1.15x, then it will just need a small change to the blakecoin top to make it work, plus using the 15.ucf rather than the 15y.ucf. Compiling it, this may take a little while.
Good luck, me know how you get on.
EDIT: I've been told (via PM) that the bitstream linked above is broken so DO NOT USE IT (now redacted, I was using the wrong hashcore, an experimental 4 core version instead of the standard 1.15y hashcore), but hal7 does have a working version which I have hosted on dropbox (bitstream link) Use --ztex-clock 128:128 for 250MHash/sec. It will probably clock a little faster (YMMV).
EDIT (9 Jan) Faster version (again courtesy hal7)
https://www.dropbox.com/s/4nnquv6z66an6c5/hal7_ztex_ufm1_15d4_2core_v02.bit
Results (min. 1h tests):
Ztex 1.15x clone - grade 2 chip: 144MHz stable with 0 HW, 6.2W power with 40mm fan
Ztex 1.15x - grade 3 chip: 152MHz stable with 0 HW, 7.0W power with 40mm fan (>300MH/s)
