I am sure the community also would like to know the following:
1) What temprature can the ASICs handle?
2) When can we expect any graphical details?
I hope BFL can answer these questions.
The range of temperature tolerance of the SC chip is extremely wide which is the nature of a dedicated ASIC as compared to a design sensitive FPGA implementation. The final temperature depends on the thermal handling characteristics of a heatsink/fan implementation. Overclocking (which is viable with the SC) will change these dynamics considerably. I think the most useful answer to your question is that the end temperature in our application as designed is around 37C, but the chips support performance stability well beyond 80C.
We will release development photos as we closer approach release.
OVERCLOCKING !?!?! So the Jalapeno could become a SC-Rig when overclocked !