Topic: ASICMINER: Entering the Future of ASIC Mining by Inventing It - page 704. (Read 3917468 times)

The meaning of this symbol was corrupted by a madman.


http://en.wikipedia.org/wiki/Swastika

yeah I find the swastika offensive.  I also found the Muslim  'jokes'   offensive.  I have no room for  that nasty stuff on this thread. 

says the guy with the swastika

Quit with the stereotyping. I find it very offending. Tefham wala la's? A7trm nafsk.

My friend my friend. This is good. Allah bless you!! ALLAHU AKHBAR!

it loks like it might be increasing, 24 hours is ~50 TH/s

Please increase hadalla hashrate . We need 18% hash plants to get better diveidends

salam!

To add to that, you always have to develop a new mask set too, even if you want to move production to another fab (unless it uses the *exact* same process which is uncommon) or even to change from a HP (fast) to a LP  (lower power) process at the same node at the same fab.

A maskset, especially at these small process nodes, is a huge cost, probably the bulk of the NRE for bitcoin asics.

If the next node is close enough (like 65->55nm) it's often possible to do so-called 'optical shrink', that is just slightly zoom the design, like how Bitfury started developing 65nm but then jumped to 55nm mid-way. However, it's usually not enough if we are switching from, say 130nm to 55nm, because distant nodes have very different physical properties, and consequently, different rules for transistor dimensions, which means that the design usually has to be heavily modified or started from scratch.

Thanks for the explanation, DeathAndTaxes. Always interesting learning about this fabrication stuff.

Nice to see these explanations on the topic!

Since we're on it, I wonder something. Sorry if I don't use the proper vocabulary...

For jumping to smaller nodes, can we reuse the same "design"? Is it what is called a mask? And does it look like a kind of map that then can be scaled to different node sizes?
In other words, how "re-usable" are the efforts invested in designing the 130nm chips when jumping to smaller nodes?

Well that is why I said only Intel is producing.  It was to highlight that Intel is "special" and gets to play by their own rules (and that has annihilated AMD margins).    I know you know that but a noob might see an Intel 14nm announcement and assume that means there will be 14nm SHA-2 ASICs "soon".

As for TSMC and 20nm it is always hard to say with the secrecy and NDA but it is looking like TSMC will have some 20nm capacity in 2014.

http://www.xbitlabs.com/news/other/display/20130806234800_TSMC_Slightly_Reschedules_Volume_Production_Using_20nm_Process_Technology_to_Early_2014.html

Everything is estimates and should be taken with a grain of salt but the estimates are moving sooner not later.  If the rumors are true though GF is struggling with 20nm.  However as we know having x nm capacity doesn't mean it is cost effective.  Nobody is going to buy 20nm Bitcoin ASICs if they cost 3x as much just because they are 20nm.  So it likely will be a "while" (2017 or later) before that becomes economical even if it is possible earlier.  The need for "double exposure" at 22nm/20nm is going to create a serious cost wall even once the marignal cost of production is significantly lower than 28nm.  It will be a high risk venture to because by the every ASIC company will be pushing 28nm product out the door with next day shipping.  Nobody is going to accept 3-6 month preorders and the huge NRE costs means a company making the jump to 22nm/20nm will need to roll out massive volume to ammortize the NRE and still remain competitive.  This time it will be the company not customers taking the risk.

Sorry first portion got chopped off.  I fixed it.

The ones in parenthesis are called half nodes.  In the early days there was just one standardized sets of process nodes.  Each one was linearly 70% of the prior node.  Remember chips are two dimensional so if you cut the length of a gate by 30% then you will cut the area by (0.7^2) by roughly half.  So each process node roughly doubles the number of transistors per square mm.

However the time between major node jumps is at least two years and later that has been slowing down.  For products which need faster improvement cycles (namely GPU) fabs began offering half node equipment.  Also it is sometimes possible for a fab to be upgraded to the half node improvement extending the ecnonomical lifespan of the chip.  Today the use of the term "half nodes" is kinda dated because many designs (like GPUs) simply upgrade only on the half node (i.e. 40nm, 28nm, 20nm).  For all intents and purposes they are just another standardized fabrication size.

As for ASICMiner vs Avalon 110nm is a different process node than 130nm.  For a given design, in theory it will result in smaller transistors, higher clock speed, and more chips per wafer. However the improvements aren't as significant as a full node jump.  If ASICMiner used 110nm instead of 130nm everything else being the same we would expect them to have ~40% higher wafer density (130nm/110nm)^2.  Still Avalon vs ASICMiner brings up a good point.  It shows that DESIGN matters a lot.  Despite the 40% "disadvantage" ASICMiner is more than competitive with Avalon.  Nothing indicates they have higher cost, energy consumption, or lower hashing density. Bitfury (55nm) chips beating KNC (28nm) is another example.  So process node matters but it is only half the equation.

Of course given the NRE costs nobody is going to make a half node jump.  Makes much more sense for ASICMiner to jump down 1 or more full process nodes.

anyone got an estimate for hardware revenue this week?

URL: http://www.businessinsider.com/intel-shows-pc-using-broadwell-14nm-chips-2013-9

DeathAndTaxes, what do the figures in parenthesis signify? I often see process nodes described like this, eg. 65/55nm. Why two figures and not one?

ASICMiner say their chips are 130nm, while Avalon say their chips are 110nm. Are the two really produced on the same process or what?

IBM is actually producing 22nm on their process for the next POWER series which available for order next year. TSMC and GloFo won't have 22nm until 2015 or 2016.

Are you trolling? 23nm fabrication doesn't exist.

Available process nodes (full process size with half size in parentheses).

130nm (110nm)
90nm (80nm)
65nm (55nm)
45nm (40nm)
32nm (28nm)
22nm (20nm) *

* Nobody is making processors @ 22nm except Intel (not even AMD or NVidia).  A couple of memory companies are using 22nm but memory is magnitudes simpler than a microprocessor.  TSMC will begin early (i.e. insanely out the butt expensive) production of 20nm in Feb 2014.

Generally it takes around 3 years before a new process node becomes cheaper than the prior node.  The only reason why cost effective 28nm Bitcoin are possible is because it is "old" tech, 28nm became available in volume production over two years ago, with early production in 2010.    Following that 3 year timeline it would put 22nm/20nm not acheiving cost parity compared 28nm until ~2017.

So 28nm is as good as it gets for the near future.  That doesn't mean we won't see improved 28nm designs but I would be willing to wager we won't see a sub 28nm Bitcoin chip (actually hashing in customer's hands) until 2017 and honestly I think it will be later than that.

23 nm?

22 nm is only available to Intel, and they don't take outside orders.