The USB 1.x and 2.0 specifications provide a 5 V supply on a single wire from which connected USB devices may draw power. The specification provides for no more than 5.25 V and no less than 4.75 V (5 V±5%) between the positive and negative bus power lines. For USB 3.0, the voltage supplied by low-powered hub ports is 4.45–5.25 V.
The usb spec, has a 5% variance. That is what I mean. But I won't be continueing in this thread anymore since you clearly taking this very personal to start attacking me for my opinion.
Topic: Best demonstrated efficiency: 1290 Mhash/Joule - page 3. (Read 20619 times)
It would not be a good idea to run a chip at 2.5 watts, a bit below 2 watts is a lot wiser, when a usb slot variance can easily dip below 2.5 watts.
Also the chip alone is not the only thing which will be drawing power, you have to take that into account, hence why the design should be below 2watts.
Also the chip alone is not the only thing which will be drawing power, you have to take that into account, hence why the design should be below 2watts.
Spec says 500mA, so you can draw 500mA. There is no such thing as "slot variance"; you are making that up...
You would be a pretty bad designer if you needed 0.5W or more to merely power ancillary logic. At most there will be a ~5-10% loss due to the 5V->Vcore power conversion (I doubt the ASIC will run on 5V). The rest (LED) should literally need 0.05W or less. Remember there is no active cooling (it's a coffee warmer). So we are talking about 2.3-2.4W available to the chip.
So If it was shrunk down to 45nm it would energy wise (optimal) result in a saving that result in about ~2 Watt chip, that does 1.25Gh/s.
Guess I wasn't that far off, when I estimated 1Gh/s for a single usb powered Chip based on a 45nm design. Still estimates, but at least an estimate I could believe.
Guess I wasn't that far off, when I estimated 1Gh/s for a single usb powered Chip based on a 45nm design. Still estimates, but at least an estimate I could believe.
More precisely, scaled to 45nm, Bit Erupter's chip would give 1.96 Ghash/s at 2.5 Watt.
This is 787 Mhash/sec and slightly better(!) than my prediction of 700 Mhash/sec for BFL's ASIC.
It would not be a good idea to run a chip at 2.5 watts, a bit below 2 watts is a lot wiser, when a usb slot variance can easily dip below 2.5 watts.
Also the chip alone is not the only thing which will be drawing power, you have to take that into account, hence why the design should be below 2watts.
Only reason why your prediction "fits" is because you just assumed they'll be using 2 usb ports to power it and also apparently going over the spec of those usb slots are capable of providing.
If BFL uses standard cell, I think they would have to go with 45nm to have chance to meet their spec.
What is the mask cost of 45nm these days?
But I figure they will go with a 45nm multiple wafer run, ie several designs on one wafer to cut down the initial cost.
They will quickly get delivery problems but now they have proven their product.
I guess the next step is to get enough preorders by then to cover the cost of a full mask set.
So If it was shrunk down to 45nm it would energy wise (optimal) result in a saving that result in about ~2 Watt chip, that does 1.25Gh/s.
Guess I wasn't that far off, when I estimated 1Gh/s for a single usb powered Chip based on a 45nm design. Still estimates, but at least an estimate I could believe.
Guess I wasn't that far off, when I estimated 1Gh/s for a single usb powered Chip based on a 45nm design. Still estimates, but at least an estimate I could believe.
More precisely, scaled to 45nm, Bit Erupter's chip would give 1.96 Ghash/s at 2.5 Watt.
This is 787 Mhash/sec and slightly better(!) than my prediction of 700 Mhash/sec for BFL's ASIC.
For those who are not following Block Erupter: Dedicated Mining ASIC Project (Open for Discussion)
Update
Our RTL design, optimization and simulation are finished. We have some data to predict the specification of actual chips after they are manufactured.
Hashrate: 1.25GH/s per chip
Area: 17.5mm^2 per chip
Power Consumption: 13.3W
Note that they are calculated from the front-end design and not accurate enough. But of course the possible difference range won't be large. We will keep our updates.
Our RTL design, optimization and simulation are finished. We have some data to predict the specification of actual chips after they are manufactured.
Hashrate: 1.25GH/s per chip
Area: 17.5mm^2 per chip
Power Consumption: 13.3W
Note that they are calculated from the front-end design and not accurate enough. But of course the possible difference range won't be large. We will keep our updates.
Fixing the url for you. Interesting numbers at 130nm, very promising as well for the future of ASIC development.
So If it was shrunk down to 45nm it would energy wise (optimal) result in a saving that result in about ~2 Watt chip, that does 1.25Gh/s.
Guess I wasn't that far off, when I estimated 1Gh/s for a single usb powered Chip based on a 45nm design. Still estimates, but at least an estimate I could believe.
For those who are not following Block Erupter: Dedicated Mining ASIC Project (Open for Discussion)
Update
Our RTL design, optimization and simulation are finished. We have some data to predict the specification of actual chips after they are manufactured.
Hashrate: 1.25GH/s per chip
Area: 17.5mm^2 per chip
Power Consumption: 13.3W
Note that they are calculated from the front-end design and not accurate enough. But of course the possible difference range won't be large. We will keep our updates.
Our RTL design, optimization and simulation are finished. We have some data to predict the specification of actual chips after they are manufactured.
Hashrate: 1.25GH/s per chip
Area: 17.5mm^2 per chip
Power Consumption: 13.3W
Note that they are calculated from the front-end design and not accurate enough. But of course the possible difference range won't be large. We will keep our updates.
Accelerators mean there are at least some custom blocks for crypto in there. I'm going to side with you and say they are just terrible engineers and couldn't find a way to get 100MH/J equivalent out of their reserved SHA2 resources. That or they reserved just a few thousand transistors for SHA2 because having the best in class performance should be reserved for real winners like BFL.
Have you considered the fact that SHA-2 in THEIR application may not require the ultimate in efficiency and even speed? 30Gbps is smoking fast for most SHA-2 applications outside of Bitcoin, and 20 watts is comparatively low-powered. I'm sure they see no reason to spend hundreds of man-hours on optimizing a small part of the overall chip design when the application that it is intended for is bottlenecked by other unrelated factors. Do you really think that BFL would be able to raise the capital necessary to do a full custom 45nm design?
I said standard cell, not full custom:
any half-decent ASIC designers should be able to take it, implement it to 45nm standard-cell tech, and get 700 Mh/J
And TSCM launched their standard-cell 45nm toolkits 5 years ago! As said earlier in this thread, this is hardly "bleeding edge" tech... The NRE costs are mostly proportional to the complexity of the chip you are designing. This is why dead-simple logic blocks (SRAM cells, NAND, etc) are always the first ones to be built at the smaller nodes (eg. 22 nm), whereas complex chips like the A5 lag behind (45 nm). A dumb SHA-256 logic block is much closer to SRAM/NAND in terms of complexity than a SoC like the A5. So I think BFL doing 45nm is absolutely plausible. But again, as I said in the OP, they may even get away with 65nm.
If that's the case then BFL would be straight lying, as they've claimed that their design is full custom.
Accelerators mean there are at least some custom blocks for crypto in there. I'm going to side with you and say they are just terrible engineers and couldn't find a way to get 100MH/J equivalent out of their reserved SHA2 resources. That or they reserved just a few thousand transistors for SHA2 because having the best in class performance should be reserved for real winners like BFL.
But if that's a 65nm or 45nm chip and the SHA2 block is allocated 1W of the power budget, shouldn't they be pulling 100+ MH/s?
No because if you read the specs of the thing you found with 30sec of googling around, you would see the Nitrox III appears to run SHA-2/RSA/etc on RISC cores (ie. a CPU core), which implies it is not a custom SHA-256 ASIC, which explains its poor performance per Joule (after all, if it was an ASIC, it should beat Spartan6 FPGAs, but it does not.)
Do you really think that BFL would be able to raise the capital necessary to do a full custom 45nm design?
I said standard cell, not full custom:
any half-decent ASIC designers should be able to take it, implement it to 45nm standard-cell tech, and get 700 Mh/J
And TSCM launched their standard-cell 45nm toolkits 5 years ago! As said earlier in this thread, this is hardly "bleeding edge" tech... The NRE costs are mostly proportional to the complexity of the chip you are designing. This is why dead-simple logic blocks (SRAM cells, NAND, etc) are always the first ones to be built at the smaller nodes (eg. 22 nm), whereas complex chips like the A5 lag behind (45 nm). A dumb SHA-256 logic block is much closer to SRAM/NAND in terms of complexity than a SoC like the A5. So I think BFL doing 45nm is absolutely plausible. But again, as I said in the OP, they may even get away with 65nm.
Do you really think that BFL would be able to raise the capital necessary to do a full custom 45nm design? I could see maybe something like American Semi's 1D 45nm process, but to do a standard 45nm full custom design just don't make sense given the market. Between late 2012 and the start of 2015 there might be 3M BTC produced. Over two years is forever in Bitcoin terms, and it might take that long for them to recover the millions in NRE.
They are (supposedly) going to be the first to market with an ASIC. Why would you attempt to fabricate on something like 45nm which is still a modern process (the A5 and Exynos 4210 in the Galaxy SII are 45nm) and pay millions in NRE? If you design at 90nm, you could still destroy the competition and sell at basically the same price points, but the NRE would be a fraction of what you'd pay at 45nm. Your time to recover those expenses would be much smaller, and your all around risk would be much lower. If later on competitors force you to a newer process you're in the driver's seat; well funded, experience and with significant brand equity.
I just can't wrap my head around them doing something like that.
They are (supposedly) going to be the first to market with an ASIC. Why would you attempt to fabricate on something like 45nm which is still a modern process (the A5 and Exynos 4210 in the Galaxy SII are 45nm) and pay millions in NRE? If you design at 90nm, you could still destroy the competition and sell at basically the same price points, but the NRE would be a fraction of what you'd pay at 45nm. Your time to recover those expenses would be much smaller, and your all around risk would be much lower. If later on competitors force you to a newer process you're in the driver's seat; well funded, experience and with significant brand equity.
I just can't wrap my head around them doing something like that.
But if that's a 65nm or 45nm chip and the SHA2 block is allocated 1W of the power budget, shouldn't they be pulling 100+ MH/s? They better hire BFL stat.
I gave you the answer already: what is consuming the bulk of their 20W power is the other logic blocks such as the RISC cores, RSA engines, etc. That's why comparing such a complex chip like the Nitrox III to a barebone SHA-2 logic block is a pointless apples vs. oranges exercise.
Or possibly reaching that energy efficiency at higher clocks *and variable protocol settings is not easy. I don't see why they wouldn't want a well balanced SHA2 logic block in their design.
Maybe you should tip Cavium that by taking an open source SHA-2 VHDL design from students/professors, and implementing it on a 12-year-old 130nm design, they could increase their energy efficiency by a factor 49x from 1.45 Mhash/J to 71 Mhash/J.
My point is: obviously Cavium did not aim at SHA-2 energy efficiency. You are comparing Apples vs. Oranges.
My point is: obviously Cavium did not aim at SHA-2 energy efficiency. You are comparing Apples vs. Oranges.
They are much bigger than BFL. 
Apples vs. Oranges.
Nitrox III implements much more than SHA-2: full-blown RISC cores, RSA acceleration, etc, blowing its TDP up.
30Gbps corresponds to 29 Mhash/s. At 20W that's 1.45 Mhash/J. Nitrox III is handily beaten by all the Spartan 6 FPGAs around here doing 20 Mhash/J. Why were you thinking that Calvium's chips were the "state of the art" in SHA-2 performance?
Nitrox III implements much more than SHA-2: full-blown RISC cores, RSA acceleration, etc, blowing its TDP up.
30Gbps corresponds to 29 Mhash/s. At 20W that's 1.45 Mhash/J. Nitrox III is handily beaten by all the Spartan 6 FPGAs around here doing 20 Mhash/J. Why were you thinking that Calvium's chips were the "state of the art" in SHA-2 performance?
I guess this 1+ Billion market cap company is slacking.
http://www.cavium.com/processor_security_nitrox-III.html
20W 30Gbps SHA2
http://www.cavium.com/processor_security_nitrox-III.html
20W 30Gbps SHA2
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