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Topic: Best demonstrated efficiency: 1290 Mhash/Joule - page 6. (Read 20540 times)

hero member
Activity: 1596
Merit: 502
If you are just looking for best Mhash/Joule I'll downclock my intel Q6600 from 2.4GHz to 2.4MHz so it is 1000 times slower and uses 1,000,000 times less energy so it gets a 1000 times better MHash/Joule rating.
mrb
legendary
Activity: 1512
Merit: 1027
Let me ask you this: if the chip measured 13.76 mJ/Gbits at 130nm, what do you think is a plausible mJ/Gbits performance figure at 32nm? how about 45nm?
donator
Activity: 980
Merit: 1004
felonious vagrancy, personified
Let me get this straight: BFL is claiming 1,750 MH/J and you are trying to say that is plausible based on some paper you found that demonstrated 71 MH/J?

Seriously?
mrb
legendary
Activity: 1512
Merit: 1027
I know. (Actually 1400 Mhash/Joule at 2.5W.) And the goal of this thread is to compare BFL's theoretical claims vs. actual chips.
legendary
Activity: 1029
Merit: 1000
Blah, BFL is talking about ~1750MH/Joule Wink Jalapeno, USB device 3.5GH/s @ 2W from USB Wink
mrb
legendary
Activity: 1512
Merit: 1027
This thread shall be used to report the best demonstrated energy efficiencies of real-world ASIC implementations of SHA-256 at the chip level.


(Note: for reference, hashing 1 gigabit of data per second corresponds to a mining speed of about 1 Mhash/s because one Bitcoin hash consists of hashing 1024 bits of data, or 2 SHA-256 data blocks: SHA-256(SHA-256(x)) minus a few SHA-256 steps that can be optimized out.)


BFL claims the 'SC' Jalapeno (3.5 Ghash/s) will be USB-powered. I theorize it will draw 5W via 2 USB ports (2.5W per port), giving it an efficiency of 700 Mhash/J. Edit: BFL has since then confirmed that the Jalapeno will be powered by 2 USB ports.

The 167 Mhash/J number at 130nm indicates that 668 Mhash/J should be possible by merely scaling down the design to 65nm (because 65nm is theoretically 4x more power efficient than 130nm as efficiency is linearly proportional to the transistor junction area), confirming my BFL estimate of 700 Mhash/J. Furthermore, it is known that BFL pre-sold $250k of SC devices in the first day, making it almost certain that they can cover the NRE cost for developing at 65nm which is only $500k. (And on top of pre-order revenues, BFL also claim to have received VC capital.)
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