Topic: BFL ASIC is bogus - page 11. (Read 22392 times)

So if it consumes 13.76 mJ/Gbit and 3.5 GH/s equals 3584 Gbit/s (512 bits block size and two of these because of double SHA-256) then a 3.5 GH/s unit running at 50 MHz would consume 49.3W - without taking into account the added power draw from a die size about ten thousand times (0.374 Gbit/s at 50 MHz vs 3584 Gbit/s) the size of the SHA-3 chip, which would be 1700mm², or 41x41mm?

Now this is 130nm, so if we're optimistic and say they have access to a 28 nm process (is this at least somewhat realistic?), then this could be reduced to 8.8x8.8mm or 78mm². Would anyone venture a guess as to what the reduced power draw from going 120nm to 28nm would be? If it's a factor 10 and, again, we ignore the added power draw from the huge die, then that gets us down to ~5W.

Or is 28nm processes currently only reserved for companies spitting out chips in the tens of millions?

Block size is actually 512 bit so it's basically 1.51 Gbps / 1024 or 1.47 MH/s
Also power goes up in a non-linear fashion as die size and clockspeed increase.

1,169.893~ rounds?

That shows Tp at the max frequency I think, while the power is at 50MHz. If you look at mJ/Gbit, that's the same as mW/Gbps. 5.18mW given 13.76mJ/Gbit would be 0.374Gbps at 50MHz. That corresponds perfectly with 1.51Gbps@200MHz.

Looking at that paper and comparing areas, it looks like the single round of SHA2 is about 3.4% of the total die size of 5mm^2, or 0.17mm^2. Think about how many rounds of SHA2 you would need at 130nm to get 3.5GH/s.
With a full custom design you'd be able to trim off some fat because you don't need to transmit every hash out, but 3.5GH/s @~5W seems very aggressive.

Someone has actually already made a chip capable of SHA-256 on an IBM 130nm process:
http://rijndael.ece.vt.edu/sha3/chip/sha3-asic-datasheet.pdf
If I understand the paper correctly, it does 2.95 MH/s (1.51 Gbps / 256 bit / 2) (divided by two because it's double-SHA-256) while consuming 5 mW (0.005 W) running at 50 MHz. So that's about 3 GH/s at 5 W on a 130nm process.

Here's more info: http://rijndael.ece.vt.edu/sha3/sha3chip.html

1) Make incredible claims about your future product promise 1 to 1 trade ins on your currently sold product
2) Point all your PR tools to talking favorably about your future product and minimizing your previous failure to meet pre-release numbers
3) Take peoples $ for future orders, this combined with money not spent due to uncertainty reduces your competitors sales and thus available funds to develop their future products
4) Some profit
5) Plow some of that money into developing something that at least might, perhaps come close to your seat of the pants PR numbers
6) ??
7) More profit

They're not making a CPU just a random number generator, I'm not sure it gets any simpler than that?

Same boat, almost :3

just placed my order on a BFL SC 40GH/s , now just to wait patiently while all my 6990's cook in my basement 

One reason to sell them cheaper might be to ensure widerspread distribution. Afterall, consolidate all that hashing into the hands of a few is suppose to be bad for bitcoin.
As for them taking only bitcoins, that is not the case. They have taken bank wires, which are traceable.

For now, I'm more interested in the power consumption question. Could ASICs do a double SHA256 hash at 3.5GH/s and be supported by only the power from a single USB port?
Are there any existing SHA256 functions performed by ASIC's that we can find specs on and determine this? This should add the weight to either it being feasability or not.

||bit

... but, isnt this the BFL forum ?

kind regards

GDammit can we move this here: https://bitcointalk.org/index.php?board=81.0

They made that subforum for a reason.

But with that, more power usage.  I doubt a USB can support that much. It barely provides any power at all.

Clearly they're lying in their press release.  They 100% won't be able to reach their performance level indicated.

The most USB 2.0 can handle is about ~2.5 Watts.  USB 3.0 is ~5 watts.

Dedicated can go up to 10 watts but ASIC is not dedicated USB charging.  Data is also fed into the ASIC.

So if the ASIC had the same hash rate as the FPGA single it has an improvement of 16x more than the FPGA at the most. Factor in the hashing, it would have ~64x improvement.

I call BS as well.  Also there's no reason for them to be selling ASICs so cheap in the first place.  It does not make sense business wise.  They will fail and run away with pre order money since Bitcoins are their only payment option and irreversible and not easy to track and crack down in the case of fradulent transactions.

Are you seeing anything in the PR that isn't consistent with current technological capability? As far as I can see, the PR hash rates can be accounted for with at least just using more ASIC chips per product.

||bit

This.

Just taking your FPGA-tested verilog and pushing it through the Synposys tools will usually get you an ASIC with 4x power improvement.

Working really hard to re-do the design from scratch will get you 8x.  Maybe 10x if you have really good engineers.

A 56x improvement in power consumption is just plain absurd.

I had the same initial assumption. It was based on some fast readings comparing FPGA and ASIC performance for similar tasks. The x3 or x4 numbers was what I was lead to think. However, not only has someone on this forum suggested that the performamnce would be orders of x10 to x50 increases from an FPGA to ASIC, but we have to consider the chips final fabric sizes. And there is still the manufacturers option on how many chips to incorporate in each product or submodule. But let's suppose just for discussion that the Jalapeno used just one ASIC chip to attain it's 3.5GH/s. And we know the FPGA Single is about 0.4GH/s per FPGA chip inside it. That means the ASIC would be about x9 faster (if it was just one chip), and consistent with the other forum person's view. So, it's much more than x3 or x4. But making the Jalapeno with just two or three such chips would mean the ASICS are x3 to x4.5 faster than the FPGA Single chips, and consistent with the other notions of performance improvement at hand. --- So,it seems it is possible by either presumed performance change per chip from FPGA to ASIC.

Aside from that, a question that I never followed up on from someone on the forums is about power consumption at those has rates. The Jalapeno, for exmaple is a USB device. How much power is required to generate that 3.5GH/s, and would a USB support it?

||bit

There have already been threads indicating that a custom ASIC on an older process could be under $1 mil USD. That being said what BFL is advertising sounds a bit too good to be true. I suppose worst case I won't mine for 2-3 months while waiting for BFL to catch up with sales/supply 

You do make me wonder about their press release. They said they had private venture capital. Which, if your $10 million number is correct, makes it hard to think someone (or some group) would have fronted that kind of money for making bitcoin mining hardware. Unless, we do not see the size of the market well enough. What is it's size?   Anyway, other than that, at least this seems exhaggerated from the BFL press release:


What are the 'some' of the 'some of the world’s great technological challenges'?  I wouldn't say that bitcoin mining is even one of the world's great technological challenges. People were doing fine mining with GPU's (even CPU's). Since those two technologies were meeting the purpose of bitcoin mining, there was no real great challenge that needed to be met.  So, they must have done some other work outside of making Singles....  Can anyone (BFL Engineer?) help elucidate what that work was?

||bit

By custom chips I mean Full Custom ASICs, that is what they are claiming they are making. That costs about 10M USD for starters.
There might be some way to get it cheaper if you have the ties but unless whoever behind BFL is some engineering wizard he doesn't even have the means to develop it.

If you know how the process of semiconductor manufacturing actually works the notation of a BFL custom ASIC is ridiculous.
To get an idea what kind of people pulled this thing off in the past... (Ninja Style ASIC development using selfwritten software), he did it: http://en.wikipedia.org/wiki/Charles_H._Moore

They do now.