Topic: BFL ASIC is bogus - page 8. (Read 22392 times)

I'm pretty sure they said they calculated they can use the heat generated from the asic for the warmer.

BFL has mentioned that the USB power is not for the mining hardware.  It's only  for the coffee warmer.  The circuit will require it's own external power supply.

and you base that on what exactly?

They promise 3.5GH per 5W (usb powered) they won't even reach that with the latest nanometer node, so the debate is irrelevant.

I was refering to full custom asics as "real" asics to which standart cell asics belong since they use the same manufactureing technique except they use tech libraries instead of construcing their own gates and sub-circuits. On the physical layer it is the same thing. FPGA conversion asics however are not, and that's the only "asic" which BFL would have access to.

Thats nonsense. The difference between a full custom asic and standard cell asic is relatively small, usually less than one process node, and we dont even know what node they used. For some applications and particularly if you dont have very skilled designers with a ton of time, a standard cell solution might even perform better, but will typically be a bit bigger.

Im pretty sure BFL will deliver a standard cell asic, and their "full custom" refers to the asic design, not the transistor design. A poor choice of words perhaps, but nothing more.

Have you even read the thread?


Except it just won't work. Again anything but a full custom asic cannot supply the promised performance. Is this some kind of wear down tactic to always come up with the same question/arguments even when they have been thoroughly answered/debunked?

Does it really matter whether it's full custom, off the shelf or in between? If it hashes at the promised level they can send me a paper towel tube wrapped in bacon with a USB port if it works.

What you are describing are fpga to asic conversions like Hardcopy.  These chips consist of the same logic layout as the fpgas you use to protoype them and they have metal layers instead of the routing fabric making them faster and cheaper to produce.

You can check out Chuck's site yourself there are some examples about what his software does.

Creating a full custom asic involves modelling the transistors, simulating the behavior of the p-n junctions and the currents through the metal layers. Next is constructing logic elements out of the transistors and configuring the layout of the chip and transferring the logic into it. There are ways to start with pre-made logic elements if you buy the software which models them for you, or rent it. There are also processes which are some in-between where you have some areas already layed out for you. There is lots of snake oil in this area... it boils down to pre-configured layers which cost you performance.

Doing some research myself, this Wikipedia article seems to suggest that HDL code is just a small part of the actual chip design (HDL code would be the "Functional Design"-step, as far as I can gather):
http://en.wikipedia.org/wiki/Physical_design_%28electronics%29

I can see I'm already way in over my head, as I don't understand most of what the article says. But it seems that my view of hardware design as "write HDL, create chip" is grossly over-simplified.

I won't be able to educate you on hardware design because I know almost nothing about this subject.

I followed Chuck Moore for a few years about creating a new multiprocessor-soc design which he actually did. (I have one of the chips at home but still haven't gotten around on using). Somewhere he mentioned that he is going to mainly pay the initial development out of his own pocket, he is trying to do it the most economical way possible and that it will be like 10mil dollars. He actually has written a entire software package including a new programming language and operating system to do it, so I'm really confident he took the cheapest route.
I don't know where exactly to find that information anymore but I will try to find and quote it. (He has blanked out some parts of his blog though)

Could you please provide some sort of evidence that backs this statement? I'm not saying you're wrong, I have no idea what these kinds of chips cost, I'm just interested in some evidence.

What would comprise the 10M figure? How much of it would be development, and how much would be payment to the fab? It looks to me like they are developing the hardware design themselves. My knowledge of this process says it's a task of creating some HDL-code, and then having this code transformed into a chip by a fab. I've also heard that you can't write generic HDL code, ie. code that fits all production processes. So they have to decide on which process to use before writing their code.

My point is this: if 90% of the production costs are related to writing the HDL-code, then it might be feasible if they are able to write the code themselves, and only need to shell out the money for the actual production.
The equivalent situation in the world of software would be a claim that says that "it costs $100,000 to develop a professional website". That may be true if you hire a web design company, who write the entire thing from the ground up, but if you're able to write the code yourself, the costs mostly comprise hosting, and not much more.

In short: please educate me about hardware design .

oh, I got it: pirate is collecting BTC to fund BFL. They will mine back the BTC with the asics.

But at what price .....

Not the same as they had with the "obviously" used single fpgas?


I think a jalapeño will barely make profit, more "barely" min it's own costs (electricity + hw)

Kintex is already available. I have seen FPGA computing boards with Kintex-7 in some tech show.

Except in the case of BFL it might turn out to be no ASIC of any kind but some next-gen FPGA like Kintex-7. That would even be consistent since BFLs main asset seems to be to be able to obtain mid-range FPGAs at wholesale prices. So they could have just made up some performance figures... you figure out the rest. (Mind you the singles were introduced to contain ASICs too.)

I don't know whats the ETA for the next-gen xilinx FPGAs but I wouldn't be surprised if it happens to coincide with the BFL deadline.

I agree that completion is good for the market, the problem is BFL isn't playing fair, neither to the market nor their customers,

As I already pointed out, I'm glad the competition isn't sleeping because current FPGA's prices are absolutely outrageous. 1 to 3.5 gmash for $150 will pull correct the current FPGA price gouging.

Don't be so sure about that, the competition isn't sleeping. And that's not the bottom line.
The bottom line if there is another fpga conversion asic before BFLs "extended" deadline people gonna be duped.

Even if the specs were 50% off, it would still demolish FPGA's and GPU's which are the only other players in the game. At 1.75 ghash @ 50 watts (50% less power, 5-10x more power) for $150, that would absolutely murder the QuadMiner which is 840 mhash @ 20 watts for $1,070. Would I be upset if they didn't meet their original marks? Sure. Would I return my preorders? No, because I certainly won't be buying a FPGA or more GPU's.

Even at my outrageous $0.25/kw rate, my 7970 can push 630 mhash at 220 watts and you can get one for $400; I'm actually more efficient now and I paid less than $300 for my 7970. Just for the power savings alone against the QuadMiner would be 180 watts or 129.6kw per 30 day month or $32.40 extra in electricity and 25% less hashing power. Based on current difficulty and BTC at $11 USD, I would make $139/month from QuadMiner and $104/month from a single 7970 or $35 less USD, add in $32.40 for electricity and that's $67.40 in lost profit and additional operating expenses. Now factor in additional capital costs of $680, and it would take me 10 months to break even (well over a year if you had cheap electricity). The question is whether you believe someone can make an ASIC in 10 months, even a "shitty" one.

Bottom line, 1) even if BFL doesn't give us near what they originally quoted, they would still reign supreme because they would still blow everyone out of the water, 2) even if BFL does not put out a single ASIC chip, the ball is already rolling and we may see ASIC's from a different vendor in a year anyways, 3) FPGA and GPU's are either running the gravy train (on us, the consumers) or just won't be worth the effort if you are in this for profit.

My take on the Jalapeno.

Nobody in his right mind would buy this for profit. This is a novelty item meant as advertisement, so people ask, : "What is that thing" Bitcoin blablabla ... ... ... ... boring ... oh and coffee.

Unlike other coffee warmer this one does not consume any additional electricity as it's being left on all the time.

As it has been speculated, that thing may come with an additional power source so it might produce more heat.

Will the heat be sufficient to warm a coffee from room temp to warmish in a few hours ? I doubt it.
 Does this thing add insignificant heat to your coffee YES.   Do I care ? NO

Well I won't be surprised if the promised specs change, but I don't think BFL can get away with changing the price point, at least not retroactively for those who have already ordered. For the original singles, the $500 price point was understood to be a special price for early adopters, with the price originally planned to go up to $600 after this. At least this is what is suggested by the following post:

https://bitcointalksearch.org/topic/m.582446

So for the original single, a price increase was on the table early in the game. Apparently at some point they raised the amount of that increase and then dropped it back. We'll see, but I will be surprised if they change price.