Topic: [LABCOIN] IPO [BTCT.CO] - Details/FAQ and Discussion (ASIC dev/sales/mining) - page 264. (Read 1079974 times)

something similar has been asked to him yesterday:

Agree.

Are you serious? How do you "physically" use libraries? They are not collections of books you know.  Sure sounds like you are the one who has no idea what he is talking about. Go here for a primer:
http://en.wikipedia.org/wiki/Physical_design_(electronics)


Synthesizing is akin to compiling code. And what you are saying is akin to software development being automated because the computer does the compilation Thats great,  now if  only you can make it write the code

Look, believe what you want. Why dont you ask TheSeven if there is a snowballs chance in hell this chip will be deployed this year. Im guessing you already did but didnt feel like posting that part.

Is it painfully obvious to anyone else that Labcoin needs to get 7 more involved in their Gen 1 project? 
  1) He's well respected.
  2) He seems to know what he is talking about and isn't afraid to admit when he doesn't.
  3) He communicates well.
  4) He is already on the payroll... use him.

Just out of curiosity, do you have any idea what people actually do with these cell libraries?  I don't mean "design the chip" but actually how they physically use them?  Because it doesn't sound like you actually have any idea.


Again, all your claims are about how long it takes to go from the start of a design to finished silicon.  None of them have to do with how late in that process they could have finalized the hardware size.  The initial choices were likely made for financial reasons, and stuck with for the same reasons.

I don't know why you're hammering this point.  You said you didn't know what you're talking about, and obviously you haven't learned anything new in the past hour.

I also asked TheSeven about this in IRC:


See that? synthesis is automated. The part that takes HDL describing the logic and generates a GDSII file containing the layers is done by computer.  If you want to generate at multiple node sizes, you can.  All you would need to do is get multiple cell libraries for different technologies, and synthesize in parallel.  It would mean less overall optimization, but you could maintain feature size flexibility up until tapeout, depending on your financial situation, since smaller nodes cost more.

This is how you actually figure things out, but the way.  If you don't know something you do research and find out.  You don't just randomly guess based on "common sense" and then argue that your random guess is correct without any evidence.

It's insignificant and shouldn't be talked about.  That's what we refer to as "satoshi dust" after dividing it by 10,000,000 shares

KnC's chip is done by orsoc. I just checked their website:

"Retargeting of complex FPGA design from Xilinx Virtex5 into an Altera Hard Copy"

Bingo. Im willing to bet that is why KnC is moving so fast (and performing so poorly on GH/W). Its not a cell based custom asic, its an altera hardcopy V. Also explains why they dont feel a need to do wafer probe testing or even final package tests.

maybe that's only one address... If you trying to hash from 2TH to 500TH its probable that you mine with a few pools from the start and don't hold all your BTC in one place...

Given the last 24 hours, the hash rate is about 300Gh/s at the mo.

It's insignificant and shouldn't even be talked about.

Another payment in.

At this point, I'm willing to assume it's really Labcoin hashing, but at a very low rate.

Tthey signed an NDA with the fab and received the cell libraries in July. Its set in stone then. Still took >2 months to tape out and until february to hash. Note that these libraries are not only specific to a node size, but to a specific process at a specific fab. What friedcat did before that would have been process agnostic, but most likely with a process node size in mind. And yes you could pick one smaller of bigger at that point, that isnt the point. The point is the 2 months it took to implement the design for their chosen process and the 7-8 months it took after tape out. But you think its ludicrous to claim that this would likely take 6-9 months.  You tell Friedcat that. And Bitfury. And BFL. IOW, everyone who so far has brought a bitcoin asic to market and even most of the one's that havent done yet but already  believe they cant do it much faster, like black arrow and cointerra.

And yes it is possible to go faster, by implementing something like altera hardcopy,  easic's nextreme, etc which is really inbetween an FPGA and a custom cell based asic. Thats the route KnC most likely took and ActiveMining definitely took. Doing that makes the development cycle substantially shorter, and has a lower NRE, but you pay for that in higher unit prices, worse performance and worse power efficiency. On 28nm thats a good tradeoff right now. But not something you can afford on a 65nm process that wont arrive until next year.


The evidence covers 100% of all other bitcoin asics. Whats your evidence it can be done substantially faster?

I hope it it's just a software glitch, not the exposed heat pad issues catching them...
perhaps they can try to under-clock the chips and learn a lesson for their 65nm version.

keep the donations coming guys they'll be the dividends people will be receiving this upcoming week

TheSeven just clarifyied something via irc from the last chat, which was already pasted here
(timestamp below is US/Central)

Once again, here is Labcoin's address

Bookmark it

https://blockchain.info/address/17psAW21J4twanAFWmbcd5WdX2pKeX3trm

Lol, wishful thinking I guess. Obviously I meant .17  

The decimal point off was in the other direction!     this adress? 17psAW21J4twanAFWmbcd5WdX2pKeX3trm

You keep talking as if the feature size for all of these chips was set in stone as soon as they started design work.  In fact if you read that post it doesn't even sound like they had picked whether they were going to do 130 or 65 nm:


It may also be possible to design a chip with die-size flexibility in mind.

You keep arguing this over and over again, claiming it takes a long time to design a chip.  No one is arguing with that. But you are presenting no evidence, and no real arguments for why it would be the case that feature size would need to be finalized early on in the design process.

All this despite the fact you've never actually designed and IC, or been involved in the process.  You're just pointing to various bitcoin chips you know about - except you don't know anything about when the feature size had to be finalized on those chips.

The evidence you're presenting is totally irrelevant to the actual claim you made.

it was

.17430599 BTC

If it was 17BTC the price would of soared by now