We would like to say thanks all to all the investors for the amount of trust being put in our venture, which led to a very successful IPO; we understand the frustration for the early issue regarding timing and shares distribution, unfortunately it depended on factors beyond our control.
These problems are now left behind and we look forward to give more detailed informations about our products and business model, we only ask to keep the thread relevant and post actual questions to let us track and reply them easily.
A big thanks to burnside and TheSwede75 for all the work done.
Sam Noi
Hi Sam,
gratulations on this IPO. There are four questions I have in mind right now and I'll start with quotes:
1. Chip specificationsAccording to the preliminary specs (
https://bitcointalksearch.org/topic/m.2664903) this chip should perform better than the BFL ASIC (65 nm) while occupying even smaller silicon area. I'm a total noob when it comes to chip designing, so can't even guess if it's possible. Any idea?
BFL - 65 nm, 16 cores, 250 MH/s each, 4 GH/s total, die size 7.1 x 7.1 mm, 12.8 W total
Labcoin - 130 nm, 16 cores, 300 MH/s each, 4.8 GH/s total, die size 6.5 x 6.5 mm, 12.8 W total
For that to be possible, not only each Labcoin core would have to be ~42% smaller [65/130*(6.5^2)/(7.1^2)] than each BFL core but also the Labcoin chip would magically operate at a higher frequency (300MHz vs 250MHz) while keeping the same power draw...
How did you achieve to create an allegedly superior chip and can you confirm those specifications?
2. 130 nm vs. newer technologyThe cost of a 28nm wafer is more or less the same as a 130nm wafer. The only real difference is NRE cost and having the expertise to develop on 28nm, that's the real bet.
Bitfury went full-custom standard cell and it worked OK for them, but that's the risk of going full-custom at first. You have the same risk, since your 130nm chip has a lot of sketchy specs. I would rather you commented on those, especially on the part where you claim to develop a faster and more power efficient chip than BFL (also standard cell) with transistors that have DOUBLE the size (130nm vs 65nm) and require much higher voltages (power consumption scales with the square of voltage).
The
graph above is for ANY ASIC manufacturer, as it compares a Normalized Transistor Cost (wafer cost + packaging + etc) to a timeline, based on yields/wafer, die sizes and wafer cost. The production costs on new die sizes quickly go down after some time.
What are the benefits to stick to 130 nm?
3. ETAIs your 130 nm chip set to being finished in
Q4 2013? Can you give a more precise time?
4. General timelineWhat are your plans for the next days and months?
By the way, I would be thrilled to see some pictures from your work and lab.
Thanks.
