While the die size determines the heat transfer at the silicon junction, the size and more importantly type of package is also important as the thermal energy must pass through the package as well and the lower the thermal conductivity the higher the core die temp is going to reach. The bizarre thing is that they reported using "QFP packaging, 44 pin, no exposed heat pad" for the size of the die that makes absolutely no sense @ >12W and is still hard to believe even at 5W. They do make packages with exposed metal heat pad to improve heat transfer. For example this is the Avalon chip.
Inside the package the die is pressed against the large square metal pad in the center of the package. The center pad is only used for heat transfer, the other pins are used for electrical power, ground, and signal. The pad will be surface mounted to a non-electrical pad (copper plate) on the PCB to conduct heat away from this chip. Using a multi-layer board the connection can extend from the top layer through the PCB to the bottom layer which is used as a heat dump. As a side note this is why the heatsink is on the "back" of an Avalon board. The heat is conducted through the heatpad, through the PCB, to the heatsink on the other side. With a QFP and no heat pad essentially the entire chip is encapsulated in insulating plastic and that greatly limits the amount of power that can be dispersed.
Inside the package the die is pressed against the large square metal pad in the center of the package. The center pad is only used for heat transfer, the other pins are used for electrical power, ground, and signal. The pad will be surface mounted to a non-electrical pad (copper plate) on the PCB to conduct heat away from this chip. Using a multi-layer board the connection can extend from the top layer through the PCB to the bottom layer which is used as a heat dump. As a side note this is why the heatsink is on the "back" of an Avalon board. The heat is conducted through the heatpad, through the PCB, to the heatsink on the other side. With a QFP and no heat pad essentially the entire chip is encapsulated in insulating plastic and that greatly limits the amount of power that can be dispersed.
I hate to say "I told you so" I never owned a share, never will I was just interested from a technology standpoint. There is a reason every other 110/130nm ASIC chip uses a heat heatpad package. If you put 12W in (and their 5W estimate was likely nonsense) you have to get 12W out. Plastic is a great thermal insulator. You aren't getting 12W out of a chip that small without something that has a higher thermal conductivity. They likely tried and with a low thermal conductivity the internal temp of the chip skyrocketed. Now they have a ton of chips which probably can't handle more than 2W which means running them at 10% speed (or slower).
