Probably the thermal tape was poorly applied, creating an air pocket that led to that. Usually the case from what I have seen. Considering the assembly quality in general and overall leakage of the thermal grease this is not a shock. It looked like a rushed job.
This is indeed problematic for a couple of reasons:
(1) There is no screw that ensures that the heat sink has some pressure against the chip.
(2) The orientation of the boards are such that the boards are vertical and therefore gravity isn't even going to work to keep the heat sinks in place.
Also, I've been saying for a while now. These heatsinks are too small.
Look at the designs of both Technobit and Dragon. They've got massive heat sinks on the chip side and it's okay even if the chips are all bunched together. Even the AMT system has a much larger heat sink than what we see here at AMT.
I can't understand the design. These are 28nm chips running on full throttle, AMT however decides to put the smallest heat sink one can imagine!
Yes, in my opinion very botched layouts. However - remember that the chips were first tested what, late Dec/early Jan? BMch and AMT had no idea of the power loads the chips would produce and had planned on it being a lot less. Technobit being a bit hobbiest-orientated had the time to deal with the real-world specs and before selling their systems had the advantage of seeing the trouble BMch ran into. Also helps that they started with 2 and 4 chip single boards to cut their teeth on.
Le sigh... To answer some question points posted, one more time thermal/power design 101:
Thermal flow of the A1 chip. Look at the A1 data sheet on Github.
70% goes out the bottom, through thermal vias on the board and then to the main heat sink on the backside. That leaves 30% out the top/sides. Obviously no one ran the math to know what that means for power in/sink capacity (inc airflow used)/chip temp on the top side much less what the die temp is based on the heatsinks used top & bottom along with their required airflows. I'd guess that like many non-design folks do they just thought 'big sink and a few smaller ones on top will be fine'...
Physical layout - "okay even if the chips are all bunched together".
No 'if'. That is how it should have been done to begin with.
It makes thermal control much easier to deal with - including overtemp sensing... (is there any?)
Same with clustering the Vcore buck inductors much closer to the chips not to mention more point-of-load filtering surrounding the chip cluster as Technobit uses. From the power standpoint, given the low voltages used distance between the Vcore supplies and the chips must be as minimal as possible to keep losses on the power planes/traces to an absolute minimum. The A1 spec says max core current is 20amps. It does *not* make any mention of spike loads - all processors have them and typically are over 2x the average running value. Spread out as everything is on the Bitmine-AMT boards I'd expect to see serious fluctations if anyone bothered to probe the chips power pins...
Use of thermal tape - really only advised if there are no shear loads put on the heatsink. If there are (gravity, g-forces) maximum permissible temps and load values must be within the mfrg recommendations or other means to secure are needed.