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[2014-08-30 05:36:53] Started cgminer 3.9.0
[2014-08-30 05:36:53] Run Reset=1
[2014-08-30 05:36:53] ST MCU hardware reset start
[2014-08-30 05:36:57] SPI Speed 4000 kHz
[2014-08-30 05:36:57] ST MCU - Enable (Pre-header)
[2014-08-30 05:36:57] A1 = 1220,9 <------
[2014-08-30 05:36:57] A1 PLL Clock = 1220MHz <------
[2014-08-30 05:36:57] A1 = 1240,8 <------
[2014-08-30 05:36:57] A1 PLL Clock = 1240MHz <------
[2014-08-30 05:36:57] A1 = 1300,5
[2014-08-30 05:36:57] A1 PLL Clock = 1300MHz
[2014-08-30 05:36:57] A1 = 1300,5
[2014-08-30 05:36:57] A1 PLL Clock = 1300MHz
[2014-08-30 05:36:57] A1 = 1300,5
[2014-08-30 05:36:57] A1 PLL Clock = 1300MHz
[2014-08-30 05:36:57] A1 = 1300,5
[2014-08-30 05:36:57] A1 PLL Clock = 1300MHz
[2014-08-30 05:36:57] AUTO GPIO CS
[2014-08-30 05:36:58] spidev0.0(cs0): Found 8 A1 chips
[2014-08-30 05:36:58] Found chip 1 with 54 active cores
[2014-08-30 05:36:58] Found chip 2 with 54 active cores
[2014-08-30 05:36:58] Found chip 3 with 54 active cores
[2014-08-30 05:36:58] Found chip 4 with 54 active cores
[2014-08-30 05:36:58] Found chip 5 with 54 active cores
[2014-08-30 05:36:58] Found chip 6 with 54 active cores
[2014-08-30 05:36:58] Found chip 7 with 54 active cores
[2014-08-30 05:36:58] Found chip 8 with 54 active cores
[2014-08-30 05:36:58] Found 8 chips with total 432 active cores
[2014-08-30 05:36:59] spidev0.0(cs1): Found 8 A1 chips
[2014-08-30 05:36:59] Found chip 1 with 54 active cores
[2014-08-30 05:36:59] Found chip 2 with 54 active cores
[2014-08-30 05:36:59] Found chip 3 with 54 active cores
[2014-08-30 05:36:59] Found chip 4 with 54 active cores
[2014-08-30 05:36:59] Found chip 5 with 54 active cores
[2014-08-30 05:36:59] Found chip 6 with 54 active cores
[2014-08-30 05:36:59] Found chip 7 with 54 active cores
[2014-08-30 05:36:59] Found chip 8 with 53 active cores
[2014-08-30 05:36:59] Found 8 chips with total 431 active cores
[2014-08-30 05:36:59] SPI(cs2) no device
[2014-08-30 05:36:59] ACK(cs2) timeout:cmd_RESET_BCAST-0.0340s
[2014-08-30 05:36:59] SPI(cs3) no device
[2014-08-30 05:36:59] ACK(cs3) timeout:cmd_RESET_BCAST-0.0325s
[2014-08-30 05:36:59] SPI(cs4) no device
[2014-08-30 05:36:59] ACK(cs4) timeout:cmd_RESET_BCAST-0.0330s
[2014-08-30 05:36:59] SPI(cs5) no device
[2014-08-30 05:36:59] ACK(cs5) timeout:cmd_RESET_BCAST-0.0409s
[2014-08-30 05:36:59] A1 boards=2, active cores=863, Efficient=99%, speed=30.0M
[2014-08-30 05:36:59] Probing for an alive pool
[2014-08-30 05:36:59] Failed to resolve (?wrong URL) /:80
[2014-08-30 05:36:59] Pool 2 slow/down or URL or credentials invalid
[2014-08-30 05:36:59] Pool 1 difficulty changed to 512
[2014-08-30 05:36:59] Switching to pool 1 stratum+tcp://xxxxx - first alive pool
[2014-08-30 05:36:59] Pool 0 stratum+tcp://xxxxxxxxxxalive, testing stability
[2014-08-30 05:36:59] Switching to pool 0 stratum+tcp://xxxxxxxxxxxxx
[2014-08-30 05:36:59] Reconnect requested from pool 0 to xxxxxxxxxxxxxxxxxxxxx
[2014-08-30 05:37:00] Pool 0 difficulty changed to 64
[2014-08-30 05:37:00] Network diff set to 235
[2014-08-30 05:37:05] Network diff set to 28.1K
[2014-08-30 05:37:05] API running in UNRESTRICTED read access mode on port 4028 (8)
[2014-08-30 05:37:05] New block detected on network before longpoll
(5s):12.02K (avg):30.77Kh/s (pool):0.000h/s | A:0 R:0 HW:0 WU:0.0/m
[2014-08-30 05:37:05] Accepted b8993e0b Diff 355/64 BA1 1 pool 0
[2014-08-30 05:37:05] Accepted b7e4d8bf Diff 356/64 BA1 0 pool 0
[2014-08-30 05:37:05] Accepted 014b4607 Diff 197/64 BA1 1 pool 0
[2014-08-30 05:37:05] Accepted a3f39325 Diff 399/64 BA1 1 pool 0
[2014-08-30 05:37:06] Accepted 01d60a79 Diff 139/64 BA1 0 pool 0
[2014-08-30 05:37:06] Accepted 01ac8489 Diff 152/64 BA1 1 pool 0
[2014-08-30 05:37:06] Accepted 014bd77a Diff 197/64 BA1 1 pool 0
[2014-08-26 04:33:05] Started cgminer 3.9.0
[2014-08-26 04:33:05] Run Reset=1
[2014-08-26 04:33:05] ST MCU hardware reset start
[2014-08-26 04:33:09] SPI Speed 4000 kHz
[2014-08-26 04:33:09] ST MCU - Enable (Pre-header)
[2014-08-26 04:33:09] A1 = 1320,4
[2014-08-26 04:33:09] A1 PLL Clock = 1320MHz
[2014-08-26 04:33:09] A1 = 1320,4
[2014-08-26 04:33:09] A1 PLL Clock = 1320MHz
[2014-08-26 04:33:09] A1 = 1300,5
[2014-08-26 04:33:09] A1 PLL Clock = 1300MHz
[2014-08-26 04:33:09] A1 = 1300,5
[2014-08-26 04:33:09] A1 PLL Clock = 1300MHz
[2014-08-26 04:33:09] A1 = 1300,5
[2014-08-26 04:33:09] A1 PLL Clock = 1300MHz
[2014-08-26 04:33:09] A1 = 1300,5
[2014-08-26 04:33:09] A1 PLL Clock = 1300MHz
[2014-08-26 04:33:09] AUTO GPIO CS
[2014-08-26 04:33:10] spidev0.0(cs0): Found 8 A1 chips
[2014-08-26 04:33:10] Found chip 1 with 54 active cores
[2014-08-26 04:33:10] Found chip 2 with 54 active cores
[2014-08-26 04:33:10] Found chip 3 with 54 active cores
[2014-08-26 04:33:10] Found chip 4 with 54 active cores
[2014-08-26 04:33:10] Found chip 5 with 54 active cores
[2014-08-26 04:33:10] Found chip 6 with 54 active cores
[2014-08-26 04:33:10] Found chip 7 with 54 active cores
[2014-08-26 04:33:10] Found chip 8 with 54 active cores
[2014-08-26 04:33:10] Found 8 chips with total 432 active cores
[2014-08-26 04:33:11] spidev0.0(cs1): Found 8 A1 chips
[2014-08-26 04:33:11] Found chip 1 with 54 active cores
[2014-08-26 04:33:11] Found chip 2 with 54 active cores
[2014-08-26 04:33:11] Found chip 3 with 54 active cores
[2014-08-26 04:33:11] Found chip 4 with 54 active cores
[2014-08-26 04:33:11] Found chip 5 with 54 active cores
[2014-08-26 04:33:11] Found chip 6 with 54 active cores
[2014-08-26 04:33:11] Found chip 7 with 54 active cores
[2014-08-26 04:33:11] Found chip 8 with 54 active cores
[2014-08-26 04:33:11] Found 8 chips with total 432 active cores
[2014-08-26 04:33:11] SPI(cs2) no device
[2014-08-26 04:33:11] ACK(cs2) timeout:cmd_RESET_BCAST-0.0336s
[2014-08-26 04:33:11] SPI(cs3) no device
[2014-08-26 04:33:11] ACK(cs3) timeout:cmd_RESET_BCAST-0.0321s
[2014-08-26 04:33:11] SPI(cs4) no device
[2014-08-26 04:33:11] ACK(cs4) timeout:cmd_RESET_BCAST-0.0314s
[2014-08-26 04:33:11] SPI(cs5) no device
[2014-08-26 04:33:11] ACK(cs5) timeout:cmd_RESET_BCAST-0.0322s
[2014-08-26 04:33:11] A1 boards=2, active cores=864, Efficient=100%, speed=32.7M
[2014-08-26 04:33:11] Probing for an alive pool
[2014-08-26 04:33:11] Pool 2 difficulty changed to 32
[2014-08-26 04:33:11] Pool 1 difficulty changed to 512
[2014-08-26 04:33:11] Switching to pool 2 stratum+tcp://xxxxx - first alive pool
[2014-08-26 04:33:11] Pool 1 stratum+tcp://xxxxx alive, testing stability
[2014-08-26 04:33:11] Switching to pool 1 stratum+tcp://xxxxx
[2014-08-26 04:33:11] Pool 0 stratum+tcp://xxxxx alive, testing stability
[2014-08-26 04:33:11] Switching to pool 0 stratum+tcp://xxxxx
[2014-08-26 04:33:11] Reconnect requested from pool 0 to xxxxx
[2014-08-26 04:33:12] Pool 0 difficulty changed to 64
[2014-08-26 04:33:13] Network diff set to 261
[2014-08-26 04:33:17] Network diff set to 28.5K
[2014-08-26 04:33:17] API running in UNRESTRICTED read access mode on port 4028 (9)
[2014-08-26 04:33:17] New block detected on network before longpoll
(5s):13.01K (avg):33.32Kh/s (pool):0.000h/s | A:0 R:0 HW:0 WU:0.0/m
[2014-08-26 04:33:17] Accepted 01177391 Diff 234/64 BA1 0 pool 0
[2014-08-26 04:33:17] Accepted 75124b09 Diff 559/64 BA1 1 pool 0
[2014-08-26 04:33:18] Accepted 01207814 Diff 227/64 BA1 1 pool 0
[2014-08-26 04:33:18] Accepted ba2b3b60 Diff 352/64 BA1 1 pool 0
[2014-08-26 04:33:19] chip(cs0) 1: invalid nonce 0x8c303900
[2014-08-26 04:33:19] Accepted e06f0d3d Diff 292/64 BA1 0 pool 0
[2014-08-26 04:33:19] Accepted 6e626f3c Diff 593/64 BA1 1 pool 0