[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 52.

ultrix

full member

Activity: 125

Merit: 100

Quote from: intron on June 09, 2013, 10:29:27 AM

Quote from: MrTeal on June 09, 2013, 10:11:16 AM

Quote from: intron on June 09, 2013, 09:21:36 AM

Last version of 'Bitfury Test Jig': http://imgur.com/5gb5qJx

Now with M3 mounting holes to fasten it to a heat sink,
1V8 - 3V3 level shifter, test pins for various signals, big
solder tabs for 0V5..0V9 core power connections and
a bit more decoupling.

It's a bi-layer and 1200x1400 mils in size (approx. 30x35 mm).

intron

Nice looking boards, but might it be better to switch to SMT connectors to keep the back flatter?

You are more than correct, but I didn't have them in my library.
And it doesn't look like there is much time for making new shapes
and such.

I thought about masking the bottom with Kapton tape to
prevent shorts with the heat sink.

intron

Approximately what I was going to do. I was thinking tape + shim the heatsink up ~2-3mm

intron

sr. member

Activity: 427

Merit: 251

- electronics design|embedded software|verilog -

Quote from: MrTeal on June 09, 2013, 10:11:16 AM

Quote from: intron on June 09, 2013, 09:21:36 AM

Last version of 'Bitfury Test Jig': http://imgur.com/5gb5qJx

Now with M3 mounting holes to fasten it to a heat sink,
1V8 - 3V3 level shifter, test pins for various signals, big
solder tabs for 0V5..0V9 core power connections and
a bit more decoupling.

It's a bi-layer and 1200x1400 mils in size (approx. 30x35 mm).

intron

Nice looking boards, but might it be better to switch to SMT connectors to keep the back flatter?

You are more than correct, but I didn't have them in my library.
And it doesn't look like there is much time for making new shapes
and such.

I thought about masking the bottom with Kapton tape to
prevent shorts with the heat sink.

intron

MrTeal

legendary

Activity: 1274

Merit: 1004

Quote from: intron on June 09, 2013, 09:21:36 AM

Last version of 'Bitfury Test Jig': http://imgur.com/5gb5qJx

Now with M3 mounting holes to fasten it to a heat sink,
1V8 - 3V3 level shifter, test pins for various signals, big
solder tabs for 0V5..0V9 core power connections and
a bit more decoupling.

It's a bi-layer and 1200x1400 mils in size (approx. 30x35 mm).

intron

Nice looking boards, but might it be better to switch to SMT connectors to keep the back flatter?

intron

sr. member

Activity: 427

Merit: 251

- electronics design|embedded software|verilog -

Last version of 'Bitfury Test Jig': http://imgur.com/5gb5qJx

Now with M3 mounting holes to fasten it to a heat sink,
1V8 - 3V3 level shifter, test pins for various signals, big
solder tabs for 0V5..0V9 core power connections and
a bit more decoupling.

It's a bi-layer and 1200x1400 mils in size (approx. 30x35 mm).

intron

toinodascoives

newbie

Activity: 52

Merit: 0

First i would like to congrat you for this nice initiative.

I dont know if you still have place for tester as i've seen so many replys but i would be happy to help.

I got experience with Pcb's , electronics circuits and ships programming and i have all the required things in topic as i work in this field and got acess to electronics labs.

BTW, i live in Europe.

nightyj

member

Activity: 89

Merit: 10

Quote from: intron on June 09, 2013, 04:42:26 AM

Test PCB layout with all above: http://imgur.com/TPcptbv

intron

Nice work intron. In this thread we talk about the final psu stage and chip itself, this is somehow wrong approach cause if we think about for the lowest parasitic parameters of the circuit without knowing the main power supply with its voltage stabiliser we can make them oscillate and emit noises because of the to low z load, so it will be good to discus also a simple power supply for a single chip. Your desing is good for cooling as you have mentioned above, if we want to acheave some better parameters we can stack bypass capacitors one on top of the other but this technique will again affect cooling performance I think that your pcb is quite good if we think just for powering up the chip and measure some parameters it will give as enough knowledge for further development.

ironcross360

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Troll of the Fourth Reich.

Im def in

Dexter770221

legendary

Activity: 1029

Merit: 1000

Indeed, great gift. My Lancelot will be happier Wink

Thanks.

bitfury

sr. member

Activity: 266

Merit: 251

Quote from: fpgaminer on June 09, 2013, 05:41:45 AM

Quote

https://mega.co.nz/#!GIF1gYZK!M_8JowhsGc6wc2b3fsRHVCdst5w8UC0M2yq1RgHwDV8

Here's source code "as is" of all my fpga-related work.

This is a wonderful gift to the community, bitfury. I'll be the first to say thank you! It is a shame that it is hidden away in a post on this forum. Do you plan to give it a proper home on your website, and/or github?

I did not see a license specified in the archive. That would be helpful to people, so they know what they are allowed to do with the code.

Congratulations on your achievement! Here's to hoping the first run of your ASICs runs as furiously as your name implies.

License - no any restrictions - do whatever you want both commercial and non-commercial.

Well - to make great announcement of bitstream - there's some docs should be written, porting, etc. really not much people can understand, maybe even some license notice if taken so seriously. I don't remember exactly to whom (but can look on skype) - but I gave it I think in Feb 2013 to people who appeared to be skilled in FPGA. and till today no results and no announce. I doubt they really wished to spend effort required :-(

fpgaminer

hero member

Activity: 560

Merit: 517

Quote

https://mega.co.nz/#!GIF1gYZK!M_8JowhsGc6wc2b3fsRHVCdst5w8UC0M2yq1RgHwDV8

Here's source code "as is" of all my fpga-related work.

This is a wonderful gift to the community, bitfury. I'll be the first to say thank you! It is a shame that it is hidden away in a post on this forum. Do you plan to give it a proper home on your website, and/or github?

I did not see a license specified in the archive. That would be helpful to people, so they know what they are allowed to do with the code.

Congratulations on your achievement! Here's to hoping the first run of your ASICs runs as furiously as your name implies.

intron

sr. member

Activity: 427

Merit: 251

- electronics design|embedded software|verilog -

Quote from: bitfury on June 09, 2013, 05:31:56 AM

Quote from: intron on June 09, 2013, 04:42:26 AM

Test PCB layout with all above: http://imgur.com/TPcptbv

I don't have Gerber files, I can just send the CAD files to the
PCB production facility. They can do boards as thin as 0.2 mm.

I don't have partnumbers for the passives yet, could be anything
I guess.

PM me please.

intron

Look - what I think about capacitors... Right in your placement with cross-section and 2 layer PCB (assuming 1.6 mm height):

4.4 mm x 1.6 mm = 7 mm^2 current loop from capacitor to power.

if you put capacitor right below chip - it would be 1.6 x 1.6mm current loop area. Roughly almost 2.8 times better.

Can't say directly inductances involved - but I believe that inductance for 4.4 x 1.6 mm current loop of this kind to be like 1.5 - 4 nH

In case if you put below the chip capacitor - it will have 0.5 - 1.6 nH additional serial inductance.

But - IF YOU USE 4-layer PCB and top layerstack would have say 0.1 mm dielectric - then current loop area would be much much less!

I just don't know your layerstack, but have this in mind - that power and ground layers should be CLOSE to each other, otherwise (if that's 2-layer pcb) - capacitors could live only on BOTTOM. Or PCB should not be thick - distance between layers affects this much.

Yes, I see that. But when bottom layer is kept free from components
the entire board can be mounted on a heat sink. Just like they did with
the Avalon Blades, have a look at the pictures. When you start mounting
stuff on layer bottom you also need a cooling device on top of the
chip. And then you migth end up where BFL is right now: Thermal Problems Galore...

This board can be bi-layer or 4-layer or whatever is needed.
I should suggest a quick, low-cost bi-layer and go from there.

intron

bitfury

sr. member

Activity: 266

Merit: 251

Quote from: intron on June 09, 2013, 04:42:26 AM

Test PCB layout with all above: http://imgur.com/TPcptbv

I don't have Gerber files, I can just send the CAD files to the
PCB production facility. They can do boards as thin as 0.2 mm.

I don't have partnumbers for the passives yet, could be anything
I guess.

PM me please.

intron

Look - what I think about capacitors... Right in your placement with cross-section and 2 layer PCB (assuming 1.6 mm height):

4.4 mm x 1.6 mm = 7 mm^2 current loop from capacitor to power.

if you put capacitor right below chip - it would be 1.6 x 1.6mm current loop area. Roughly almost 2.8 times better.

Can't say directly inductances involved - but I believe that inductance for 4.4 x 1.6 mm current loop of this kind to be like 1.5 - 4 nH

In case if you put below the chip capacitor - it will have 0.5 - 1.6 nH additional serial inductance.

But - IF YOU USE 4-layer PCB and top layerstack would have say 0.1 mm dielectric - then current loop area would be much much less!

I just don't know your layerstack, but have this in mind - that power and ground layers should be CLOSE to each other, otherwise (if that's 2-layer pcb) - capacitors could live only on BOTTOM. Or PCB should not be thick - distance between layers affects this much.

intron

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Activity: 427

Merit: 251

- electronics design|embedded software|verilog -

Quote from: bitfury on June 08, 2013, 09:56:04 AM

1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

2. IOVDD is hanging. IOREF is IOVDD/2. should be 1.8V at most (dielectric will likely broke at 2.5 V).

3. OUTCLK is likely would be difficult to send 'off-board', but at least it should be accessible as test-pin, to check if internal oscillator is running.

4. Can you give me gerbers and materials information - I'll check it with tools ?
I need from you layer stack description (i.e. I expect that this is FR4 and 1.6 mm board). I think that's too thick and better to have it thinner, if possible on 0.5 mm at most... but I would like to check.
Also I think that it could need different set of capacitors including smaller ( 0402 ) ones. I would like to check |Z| and see if it is fine or not.

Please give me part number of capacitor that you intended to place there (that say you intially have).

PS. And please treat chips with care - ESD properties are not known!

Test PCB layout with all above:

I don't have Gerber files, I can just send the CAD files to the
PCB production facility. They can do boards as thin as 0.2 mm.

I don't have partnumbers for the passives yet, could be anything
I guess.

PM me please.

intron

bitfury

sr. member

Activity: 266

Merit: 251

2 Swede - I answered.

Decided to post spectrum of current consumed within chip. That's FFT transform of current value ( I(t) ). In this modelling run it was delivered using ideal power rails (no resistance and capacitance and ideal voltage source). At test clock of 100 Mhz. As one half of cores works on positive edge while other of negative edge - you should see that most of current is consumed at 2xfclk.

Model voltage is 0.6 V, typical-typical nmos-pmos transistors with parasitics, 8 cores (of 756!).
You should see there's three portions:

1) 2*fclk and harmonics - highest current spikes;
2) high-frequency part in range of 3 to 8 Ghz - that's rise/fall times.
3) lower than 2*fclk - that's because of differences in computation load, not much, but - it will likely excite resonances.

TheSwede75

full member

Activity: 224

Merit: 100

Bitfury,
Can you confirm you received my pm. I am very interested in participating both personally and through contacts with bitcoin miner start-up connections. I will pm you my address.

monguru

newbie

Activity: 15

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Be in touch! Cheesy

I am Electrical Technician, with knowledge, equipment and programming experience!

And most importantly, I am free fully dealt with in the project!

Thank you!

intron

sr. member

Activity: 427

Merit: 251

- electronics design|embedded software|verilog -

Quote from: bitfury on June 09, 2013, 02:59:28 AM

Quote from: intron on June 09, 2013, 02:38:04 AM

Quote from: bitfury on June 08, 2013, 12:35:58 PM

Also don't forget about level shifters - i/O is 1.8 V not 3.3 V (!!!).

Are the inputs 3V3 tolerant? This means, can they be fed
directly from a processor that is powered with 3V3? Then
'level shifting' could be no more then inserting a series resistor.

intron

Should not be tolerant according to specs, oxide thickness is good for 2.0 V for long period.. Although it may tolerate 2.5V as well or even 3.3V - that's not recommended by foundry.

There's also ESD-protection diodes that will open and deliver current to IOVDD pin in this case - their Vth is about 0.6-0.7 V.

So if IOVDD is about 1.2 or 1.4 V - then it's safe! If higher - performance and reliability may vary.

Ok, put it in the schematic.

bitfury

sr. member

Activity: 266

Merit: 251

Quote from: intron on June 09, 2013, 02:38:04 AM

Quote from: bitfury on June 08, 2013, 12:35:58 PM

Also don't forget about level shifters - i/O is 1.8 V not 3.3 V (!!!).

Are the inputs 3V3 tolerant? This means, can they be fed
directly from a processor that is powered with 3V3? Then
'level shifting' could be no more then inserting a series resistor.

intron

Should not be tolerant according to specs, oxide thickness is good for 2.0 V for long period.. Although it may tolerate 2.5V as well or even 3.3V - that's not recommended by foundry.

There's also ESD-protection diodes that will open and deliver current to IOVDD pin in this case - their Vth is about 0.6-0.7 V.

So if IOVDD is about 1.2 or 1.4 V - then it's safe! If higher - performance and reliability may vary.

intron

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Activity: 427

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- electronics design|embedded software|verilog -

Quote from: ecliptic on June 08, 2013, 06:46:06 PM

And reading through your posts in this thread I can tell you really know your stuff. Very much the opposite of BFL.

LOL:) Very much so...

intron

sr. member

Activity: 427

Merit: 251

- electronics design|embedded software|verilog -

Quote from: bitfury on June 08, 2013, 12:35:58 PM

Also don't forget about level shifters - i/O is 1.8 V not 3.3 V (!!!).

Are the inputs 3V3 tolerant? This means, can they be fed
directly from a processor that is powered with 3V3? Then
'level shifting' could be no more then inserting a series resistor.

intron

Topic: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 52. (Read 176729 times)