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Topic: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 53. (Read 176727 times)

sr. member
Activity: 266
Merit: 251
I’d love to check out his design philosophy, anyone got a link?

https://mega.co.nz/#!GIF1gYZK!M_8JowhsGc6wc2b3fsRHVCdst5w8UC0M2yq1RgHwDV8

Here's source code "as is" of all my fpga-related work.

There's hardmacro placer and
btcser is core that gave 300 Mh/s+
and
different other tries - say 4 sha256 fully unrolled cores example.

I have given sources already to some people expecting them to make bitstreams for say ZTEX boards, but it seems that they failed to understand what there is.
You may try to accomplish that if you're good enough. Or may forward it to those who you believe are good enough and would like to spend time on this.
I promised actually long time ago to make it opensource, so I am keeping this promise, but unfortunately to make it usable it should be ported to other
device interface and I don't have time to do that.

BTW, asic layout some time in the future will be opensourced as well. So this will be likely end-game against any competition here, as when they get to master full-custom layout - it will become opensource stuff Smiley
newbie
Activity: 28
Merit: 0
How many cores are in the chip and how many clock cycles does it take to get a result?
Does each core has GPIO or is there some serial but that aggregates them?
Does your QFN48 7x7mm packaging has exposed thermal pad and is it on top or bottom?

1. 756 double sha256 cores. 61+4 kernel (61 clock cycle computation 4 clock cycle load).

2. There's asynchronous 'match' signal - the only thing that core sends out. And some busses to load data.

3. wirebond. die is laid normally in cavity. i.e. it is not flip-chip and not arranged to give heat into anything else, but PCB.
It is actually not complex to dissipate 3W... Maybe even 5W with metal-core PCB and proper cooling. That's what we'll see.

756 double cores in 7x7mm package?, how many gates approximately in each double core and what are the die dimensions?
You should probably read a little on the design philosophy bitfury used in his previous FPGA design. I believe he fit 82 cores in an LX150.

I’d love to check out his design philosophy, anyone got a link?
sr. member
Activity: 406
Merit: 250
member
Activity: 76
Merit: 10
sr. member
Activity: 266
Merit: 251
To ALL - I would give EXAMPLE how to model bypass network using SiWave, and that it is not that easy as many may think, compared to powering low power consumption circuits:

http://home.educities.edu.tw/oldfriend/article/PI/PI%20and%20GND%20bounce%20sim.pdf

In our case say of dead-bug - it is simpler as many PCB effects are neglected and wirebond inside of package is more like genuine inductor, so lumped circuit calculation should be fine.
With PCB that's more complex. If you would have spectrum analyzer and tracking generator at hand, you could at least verify what you do. Because if you introduce say 2 nH per VDD pin
additionally with PCB - that's very crap job - because you can put a lot of capacitors and they will work MUCH WORSE than 5 0402 capacitors put right in dead-bug style. Also there can
be parasitic resonances as you see in that PDF file that are caused with PCB layerstack itself. For homebrew PCBs vias also issue - one way to go is to make vias smaller, more vias and
to use PCM material say of 0.5 mm thickness. It is fragile, but EM characteristics should be good.

It's too bad you didn't put the bet on a site run by someone reputable.
I'm ineligible just because that one is run by a troll.

In any case, I don't see any reason why I can't offer to provide remote software-end support for anyone who has the hardware skills but needs someone on the software end.
Send me a PM if interested.

Well. Personally I have no objections. AFAIK this is related to BFL testing, maybe bets. So maybe they have reasons to not trust your verifications - I don't know.
But there's maaany requests to do testings, I'll talk to Niko how we'll proceed. I'll ask whether he could send more packages or not. Will come here shortly. We can send to
10 location likely easily. Sending more chips is not problem by regular mail but it will be delayed of course. Waiting when he wake up in Taipei. By the way you know him.

OK. I'll have delay here, I think Niko will catch up, while I will work to prepare spi user-space code for raspi and check it with logic analyzer for correctness - it will send some test-vectors
to chip and wait for the result (found nonce). That is sufficient chip. Miner would be next stage. Right now don't want to introduce more issues.
donator
Activity: 2352
Merit: 1060
between a rock and a block!
legendary
Activity: 2576
Merit: 1186
It's too bad you didn't put the bet on a site run by someone reputable.
I'm ineligible just because that one is run by a troll.

In any case, I don't see any reason why I can't offer to provide remote software-end support for anyone who has the hardware skills but needs someone on the software end.
Send me a PM if interested.
sr. member
Activity: 322
Merit: 250
Interesting.

Still reading through but I'm very interested in getting some chips

I'm an Electrical Engineer in the USA and have access to spectrum analyzers, oscilloscopes, power supplies, clock generators, FLIR camera/fiber optic thermometers, etc that would be needed to properly test these chips and quantify their performance in an objective way.  I can design PCBs and then mill or order them from a board house as well

I haven't seen anything about the hardware, if there's a reference PCB design or we should create something, but I'd be able to do that myself.  Soldering I could do by hand or have them pick & place + reflowed to build the PCB Assemblies.

You say it's QFN, do you have a thermal pad on the bottom similar to Avalon's design or is your heatsinking provided with an external heatsink on the top?

In the spirit of disclosure - If you look through my posts I've spent my time working on the Avalon chips and have purchased a number of them and am doing similar work on the PCB assemblies for those.  I was aware of the bitfury project but being unable to read russian (which it seems most of the material is in) and the difficulty to get the chips outside of Russian i was wary.  I would put together quantitative, objective measurements of these chips to allay fears and concerns of the community and myself

And reading through your posts in this thread I can tell you really know your stuff.  Very much the opposite of BFL.  The power supply decoupling (and buck converter supplies themselves) and associated PCB routing for the chips is critical.  Deadbug would be fastest but the parasitic ESL may very well limit performance.

Ok, i see you say they're designed to dissipate heat into the PCB (e.g. thermal pad like Avalon, i'm assuming you have a lot of insulator so putting a heatsink on top is pointless, like avalon design).  Have you tested these chips deadbug'd?  sounds like it may require some careful heatsink mounting to the pad to run at full power dissipation
member
Activity: 83
Merit: 10
I am interested.
I am a Geekdom member (Code and Hardware hacker space) space in San Antonio, TX.
I think this might be a interesting project for more than a few.


JR
legendary
Activity: 2128
Merit: 1073
EXCELLENT JOB! Now trick is to actually solder together VDD pins and put proper capacitors between GND pad and VDD pads connected. Then solder to central pad THICK wire - interesting how that could be done (as heat sink). Initially I thought that it must be done with hot air after capacitors soldered and chip is held.... wires would be soldered as last step as it would be hard to solder to thermal pad if you have thick wire there.

One of the ways how to do - take thick wire - say 16 sq.mm, solder it from one side thoroughly, cut (remove also insulation if any) - say leave 50mm of wire length... Then - heat wire first while holding it with pliers, then heat chip and wire togeher and connect them. Then you'll have to cool this with air and then spread copper wires and you'll get heatsink.
I've seen QFN-packaged parts soldered to the top of a thick brass/copper bolt, e.g. for a 7mm*7mm package use 5mm diameter bolt. That wasn't done for cooling, it was hand-made modification while doing a thermal characterization/calibration of a mixed-signal SoC.

It looked like a high-current diode, but was neither high-current nor high-frequency, just a way to reduce the inherent internal heating of the SoC executing the boot / self-test / calibration program.

Edit: Actually I misremembered, the bolts were made of phosphor bronze. I don't know how easy would be to obtain such parts. They aren't expensive, but are considered "specialty" / "non-stock" / "special order" items.
sr. member
Activity: 335
Merit: 250
full member
Activity: 121
Merit: 100
I'm registering my interest as a tester.

I own a Raspberry Pi and understand C.
I do not own a lab power supply. I would have to order parts from Digikey (which takes 2 days for me to get parts from).
I can generate a clock signal up to ~300 MHz (I think) using FPGA DCM.
I only have a 100 MHz DSO.
I have the ability to etch my own PCBs.
I own a soldering and SMD rework station.

Thank you.
legendary
Activity: 1274
Merit: 1004
Dead bug? Plenty of QFN Adapters available with next day delivery. May need to drill out centre to access ground pad though.

If you check the pinout, the only ground is the bottom pad. You could use a surfboard and it would be much easier, but you would have to be pretty creative to mount bypass caps close to the pins as there aren't any grounds on the top of the PCB.
full member
Activity: 196
Merit: 100
Dead bug? Plenty of QFN Adapters available with next day delivery. May need to drill out centre to access ground pad though.

[Edit] Oops, just noticed nightyj post above, I should read entire thread before posting,  Embarrassed
Don't buy from ebay though. Use Digikey, RS, Farnell etc.
sr. member
Activity: 266
Merit: 251
Even a 0.5mm pitch QFN isn't that tough to dead bug. This took about 20 minutes and it's a 0.5mm pitch QFN24. Forgive the crappy iPhone photos.
I agree though, properly mounting the chips would be best. There's really no reason not to, other than the turnaround of a week raising the price of a PCB. Even buying a surfboard would be better (and easier).

EXCELLENT JOB! Now trick is to actually solder together VDD pins and put proper capacitors between GND pad and VDD pads connected. Then solder to central pad THICK wire - interesting how that could be done (as heat sink). Initially I thought that it must be done with hot air after capacitors soldered and chip is held.... wires would be soldered as last step as it would be hard to solder to thermal pad if you have thick wire there.

One of the ways how to do - take thick wire - say 16 sq.mm, solder it from one side thoroughly, cut (remove also insulation if any) - say leave 50mm of wire length... Then - heat wire first while holding it with pliers, then heat chip and wire togeher and connect them. Then you'll have to cool this with air and then spread copper wires and you'll get heatsink.


Yes, with how you laid out the pins it should actually be relatively easy. As you say, just use a bus for Vdd across the entire row of Vdd with a few 0402 capacitors to the thermal pad. You could either use a thick wire to connect Vss, or use an array of pins. I was planning on using maybe 4-6 of the pins from a 2mm header as the ground, since that would give you a decent bit of surface area that you could run a fan across them.

Great idea! Yeah - with pin layout - I did layout thinking of strings of chip assembly and did most of redistribution inside of chip, having in mind that for example it could fit on metal-core PCB when you don't have many layers. So wires should be straight there. If everything is wired correctly Smiley

I'm putting together a PCB for testing, but I'll have to see whether it's reasonable to get it fabbed and shipped to me at a reasonable cost by Thursday. What is the max SPI speed supported by the chip?

Well - with PCB take care of capacitor impedance. I doubt that thick 2-layer PCB will work better than capacitors you put there. I'll give you model:

1) Internal capacitance is about 50 nF
2) wirebond single VDD wire is about 1.5 - 1.8 nH
3) wirebond to GND is about 0.04 nH

total VDD+GND wirebond inductance is about 0.08 nH
resonant frequency of this internal LC-tank is about 70 Mhz.

Make at least ESL (serial inductance) to capacitors to about the same - of 0.08 nH
If you have 0402 and place it really well - it would have about 0.4 nH inductance - so put at least 5 of them there. But depends on your capacitors actually, they're a bit different.
Then if your power supply is far away (lab power supply) - I would put somewhere there 1 or 2 tantal caps and maybe some 0805 caps. But to calculate actual numbers - err - should do math - for frequencies up to say 100 Mhz here lumped circuit and it is pretty straightforward to calculate by hand using complex amplitudes... not slept too long, unfortunately will not do now :-)
The overall idea of power supply is to get |Z|(w) adequate low value, and rather flat without increasing peaks at specific frequencies that will be excited when chip average consumption changes a bit cycle to cycle (this is what I would like actually to see - how power consumption spectrum looks like). Also beware of parasitic resonances when different caps are placed (C - L - C) - that's why I offered such analysis.

Inside chip there's largest power consumption spike is 200-300 ps current risetime with target of about 8 amps, while average consumption is about 4 Amps for 0.8 V. It's pretty tought. As the more ripple on internal VDD ==> less clock you'll have or at low voltages flip-flops can loss data.

To sum up - I can't say if it will work as expected in say on 2-layer pcb with big homemade vias and large distances between caps and chip it will work as expected. Much more capacitors shall be installed with less efficiency.
Please note that small capacitor works as INDUCTOR at high frequencies... Not as capacitor... it shorts higher frequencies as small INDUCTOR would. INDUCTANCE IS PROPORTIONAL TO CURRENT PATH AREA (!!!). So - having larger distance between planes + larger distance for electrons to flow from your capacitors and they will flow without being happy and will do their job of calculating hashes lazily, so to keep them happy - reduce number of inductors on their way!
legendary
Activity: 1274
Merit: 1004
You can order experimental pcbs with cooling pads such as http://www.ebay.com/itm/PCB-adapter-for-QFP44-or-QFN44-package-/161025491663?pt=UK_BOI_Electrical_Components_Supplies_ET&hash=item257dde02cf .
I am planing to order my pcbs at the local pcb assembly factory to make accurate testing, cause testing with long wires and no pads under the chips will give a lot different operation results from the real pcb working enviroment.

I'm not so much talking about doing thorough chip testing and trying to see what is possible, I'm looking at what would need to be done on a single chip in order to have results posted by next Friday afternoon. I don't have any QFN/QFP48 ones laying around, so you'd have to make sure you can get them in by Thursday or so.
member
Activity: 89
Merit: 10
You can order experimental pcbs with cooling pads such as http://www.ebay.com/itm/PCB-adapter-for-QFP44-or-QFN44-package-/161025491663?pt=UK_BOI_Electrical_Components_Supplies_ET&hash=item257dde02cf .
I am planing to order my pcbs at the local pcb assembly factory to make accurate testing, cause testing with long wires and no pads under the chips will give a lot different operation results from the real pcb working enviroment.

About the cooling wire that you plan to add solder to the chips pad it is better to be added first cause it will need a lot of heating and can resolder the other wires, once the big wire is soldered it will be even easirer to solder the others cause this wire can also act like stand.
legendary
Activity: 1274
Merit: 1004
Even a 0.5mm pitch QFN isn't that tough to dead bug. This took about 20 minutes and it's a 0.5mm pitch QFN24. Forgive the crappy iPhone photos.
I agree though, properly mounting the chips would be best. There's really no reason not to, other than the turnaround of a week raising the price of a PCB. Even buying a surfboard would be better (and easier).

EXCELLENT JOB! Now trick is to actually solder together VDD pins and put proper capacitors between GND pad and VDD pads connected. Then solder to central pad THICK wire - interesting how that could be done (as heat sink). Initially I thought that it must be done with hot air after capacitors soldered and chip is held.... wires would be soldered as last step as it would be hard to solder to thermal pad if you have thick wire there.

One of the ways how to do - take thick wire - say 16 sq.mm, solder it from one side thoroughly, cut (remove also insulation if any) - say leave 50mm of wire length... Then - heat wire first while holding it with pliers, then heat chip and wire togeher and connect them. Then you'll have to cool this with air and then spread copper wires and you'll get heatsink.


Yes, with how you laid out the pins it should actually be relatively easy. As you say, just use a bus for Vdd across the entire row of Vdd with a few 0402 capacitors to the thermal pad. You could either use a thick wire to connect Vss, or use an array of pins. I was planning on using maybe 4-6 of the pins from a 2mm header as the ground, since that would give you a decent bit of surface area that you could run a fan across them.

I'm putting together a PCB for testing, but I'll have to see whether it's reasonable to get it fabbed and shipped to me at a reasonable cost by Thursday. What is the max SPI speed supported by the chip?
sr. member
Activity: 266
Merit: 251
2 MrTeal: there's amplifier circuitry between core and iO voltage. What I don't know is power-up sequence - should be not important (i.e. no latch up) - but unsure.
So IOVDD can be 1.8V while VDD is 0.5 V -  no problem.

I've studied the protocol a bit more. It's about as bare-bones as it gets. No return code checks. Smiley

So, if I understand correctly, if chaining is 'on' you will always address all the chips in the chain by setting the address to the address of the first chip on the bus. If  chaining is 'off' you set the address to that of the individual chip. If there is a broken chip you can still use the bus up to the point of the broken chip by setting the length parameter accordingly.

To understand better - there's component

INPUT ---> [ SPICTRL ] ---> OUTPUT
                      |
                      v
                 INTERNALS

Mesage is routed to internals only when DATA transmission is done - it basically sets address and executes bits programming data on setup addresses.
In case if chip is intermediary - it just propagates DATA from input to output and does not modify internal state, same for prefix instructions, so consider it as programmable SPI switch component.

It would be good to develop a test suite on top of this that would exercise chains of different lengths - single, double, 4x, etc. Is there a maximum expectation of chain length?

depends much on failure rates. Actually SPI has lower probability of failure than say cores - as SPI is made of really big cells, looking more like 180nm using 65nm rules. Say 4 vias duplication on every wire there. Also SPI is small
so overall yield should be good.

I guess if you don't get a dead chip in your batch you have to sacrifice one to test the test suite. Tongue

well - it depends on failure actually... how I should take it down...
legendary
Activity: 1274
Merit: 1004
1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

There is no PLL on board? Feeding many chips with
"not less then 100 MHz" over the entire board can
be quite challenging.

intron


There's no PLL on board. There's two kinds of self-running internal oscillators based on programmable delays, but these may fail or give bad performance. It is quite sensitive things. So for testing I left INCLK pin.
Likely it should not be used (INCLK). But OUTCLK likely will be used to test internal oscillator frequency, whether it changes too much or have artifacts.

Putting 500 Mhz isn't big deal if you have good impedance matching. Same is for output. But to chain high speed clock - you have to setup carefully voltage at IOREF pin (even without chain!) so you get duty cycle captured correctly.
Parameters is what I am currently worried.  100 Mhz is even easier. Just have in mind that at such frequencies on short lines on PCB you work likely in LC-mode of transmission line with all of the consequences, maybe even RC-line, depending on its length!

Also don't forget about level shifters - i/O is 1.8 V not 3.3 V (!!!).


Are there any restrictions on IOVDD when trying to run the chip with VDD at 0.5V?
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