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Topic: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 54. (Read 176729 times)

sr. member
Activity: 266
Merit: 251
Even a 0.5mm pitch QFN isn't that tough to dead bug. This took about 20 minutes and it's a 0.5mm pitch QFN24. Forgive the crappy iPhone photos.
I agree though, properly mounting the chips would be best. There's really no reason not to, other than the turnaround of a week raising the price of a PCB. Even buying a surfboard would be better (and easier).

EXCELLENT JOB! Now trick is to actually solder together VDD pins and put proper capacitors between GND pad and VDD pads connected. Then solder to central pad THICK wire - interesting how that could be done (as heat sink). Initially I thought that it must be done with hot air after capacitors soldered and chip is held.... wires would be soldered as last step as it would be hard to solder to thermal pad if you have thick wire there.

One of the ways how to do - take thick wire - say 16 sq.mm, solder it from one side thoroughly, cut (remove also insulation if any) - say leave 50mm of wire length... Then - heat wire first while holding it with pliers, then heat chip and wire togeher and connect them. Then you'll have to cool this with air and then spread copper wires and you'll get heatsink.
sr. member
Activity: 266
Merit: 251
1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

There is no PLL on board? Feeding many chips with
"not less then 100 MHz" over the entire board can
be quite challenging.

intron


There's no PLL on board. There's two kinds of self-running internal oscillators based on programmable delays, but these may fail or give bad performance. It is quite sensitive things. So for testing I left INCLK pin.
Likely it should not be used (INCLK). But OUTCLK likely will be used to test internal oscillator frequency, whether it changes too much or have artifacts.

Putting 500 Mhz isn't big deal if you have good impedance matching. Same is for output. But to chain high speed clock - you have to setup carefully voltage at IOREF pin (even without chain!) so you get duty cycle captured correctly.
Parameters is what I am currently worried.  100 Mhz is even easier. Just have in mind that at such frequencies on short lines on PCB you work likely in LC-mode of transmission line with all of the consequences, maybe even RC-line, depending on its length!

Also don't forget about level shifters - i/O is 1.8 V not 3.3 V (!!!).
member
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Nice work, I am in for testing, pm sent.
hero member
Activity: 518
Merit: 500
BTC < > INR & USD
Reserved and Observing.!
legendary
Activity: 1274
Merit: 1004
1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

There is no PLL on board? Feeding many chips with
"not less then 100 MHz" over the entire board can
be quite challenging.

intron


I'd agree with this, initial testing on one chip should be fine. I have an Agilent AFG3252 so I'd be limited to a max of 240MHz but I don't imagine I would be able to hit that without without reasonable cooling anyway. Running a 500MHz clock at full speed around a board to multiple chips is a bit of a concern. Did you envision using multiple external PLLs for each group of ASICs?
sr. member
Activity: 280
Merit: 250
legendary
Activity: 1176
Merit: 1001
CryptoTalk.Org - Get Paid for every Post!
I've studied the protocol a bit more. It's about as bare-bones as it gets. No return code checks. Smiley

So, if I understand correctly, if chaining is 'on' you will always address all the chips in the chain by setting the address to the address of the first chip on the bus. If  chaining is 'off' you set the address to that of the individual chip. If there is a broken chip you can still use the bus up to the point of the broken chip by setting the length parameter accordingly.

It would be good to develop a test suite on top of this that would exercise chains of different lengths - single, double, 4x, etc. Is there a maximum expectation of chain length?

I guess if you don't get a dead chip in your batch you have to sacrifice one to test the test suite. Tongue
legendary
Activity: 1274
Merit: 1004
Even a 0.5mm pitch QFN isn't that tough to dead bug. This took about 20 minutes and it's a 0.5mm pitch QFN24. Forgive the crappy iPhone photos.



I agree though, properly mounting the chips would be best. There's really no reason not to, other than the turnaround of a week raising the price of a PCB. Even buying a surfboard would be easier.
sr. member
Activity: 427
Merit: 251
- electronics design|embedded software|verilog -
1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

There is no PLL on board? Feeding many chips with
"not less then 100 MHz" over the entire board can
be quite challenging.

intron
sr. member
Activity: 378
Merit: 250
Single chips is quick & dirty. Yes I want more - ideally I would like to see board that is powered with 12 V strings and have no external components (costs) except chips and passive components.
But that won't be simple to get. But that's what I was aiming to actually blow off any other component vendors from bill of materials and do not make bottlenecks with turn-around-times and such with inductors, many power regulators and such.
But this is what again - likely can't be done quicky, only if very lucky and there should be no complex filtering/anti-resonance issue between chips in a string (you see - we now connect CMMINUS, CMQ, CMPLUS to GND).

bitfury,

We designed an ASIC miner called S-HASH, hosting 16 Avalon chips.

See: http://imgur.com/74CHJVv

Reworking it to new ASICs won't take that long.

Our boards will arrive somewhere this coming week.

intron.

hi intro

can you upload you cad files somewhere?

sr. member
Activity: 427
Merit: 251
- electronics design|embedded software|verilog -
Single chips is quick & dirty. Yes I want more - ideally I would like to see board that is powered with 12 V strings and have no external components (costs) except chips and passive components.
But that won't be simple to get. But that's what I was aiming to actually blow off any other component vendors from bill of materials and do not make bottlenecks with turn-around-times and such with inductors, many power regulators and such.
But this is what again - likely can't be done quicky, only if very lucky and there should be no complex filtering/anti-resonance issue between chips in a string (you see - we now connect CMMINUS, CMQ, CMPLUS to GND).

bitfury,

We designed an ASIC miner called S-HASH, hosting 16 Avalon chips.

See:



Reworking it to new ASICs won't take that long.

Our boards will arrive somewhere this coming week.

intron.
sr. member
Activity: 266
Merit: 251
Single chips is quick & dirty. Yes I want more - ideally I would like to see board that is powered with 12 V strings and have no external components (costs) except chips and passive components.
But that won't be simple to get. But that's what I was aiming to actually blow off any other component vendors from bill of materials and do not make bottlenecks with turn-around-times and such with inductors, many power regulators and such.
But this is what again - likely can't be done quicky, only if very lucky and there should be no complex filtering/anti-resonance issue between chips in a string (you see - we now connect CMMINUS, CMQ, CMPLUS to GND).

Thanks. A quick draw of a bitfury test jig can be found here: http://imgur.com/iLbdViD

intron

1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

2. IOVDD is hanging. IOREF is IOVDD/2. should be 1.8V at most (dielectric will likely broke at 2.5 V).

3. OUTCLK is likely would be difficult to send 'off-board', but at least it should be accessible as test-pin, to check if internal oscillator is running.

4. Can you give me gerbers and materials information - I'll check it with tools ?
I need from you layer stack description (i.e. I expect that this is FR4 and 1.6 mm board). I think that's too thick and better to have it thinner, if possible on 0.5 mm at most... but I would like to check.
Also I think that it could need different set of capacitors including smaller ( 0402 ) ones. I would like to check |Z| and see if it is fine or not.

Please give me part number of capacitor that you intended to place there (that say you intially have).

PS. And please treat chips with care - ESD properties are not known!
full member
Activity: 224
Merit: 100
sr. member
Activity: 427
Merit: 251
- electronics design|embedded software|verilog -
Trying to get my head around the protocol now, questions will come later.

Pff, I'm glad I'm not the only one having a hard time
understanding this here:)
legendary
Activity: 1176
Merit: 1001
CryptoTalk.Org - Get Paid for every Post!
bitfury,

Trying to get my head around the protocol now, questions will come later.

A question for now: For the purposes of alpha-testing do you want us to demonstrate chaining or just put a single chip through its paces? Obviously testing a single chip is going to be faster and easier, but you probably want more.
sr. member
Activity: 427
Merit: 251
- electronics design|embedded software|verilog -
IOVDD - feed it with 1.8 V
--
This is for IO with the processor I guess? Can it be 3V3 also?

INCLK - input clock (in case if internal oscillator not works)
--
What clock frequency?

INMOSI, INSCK - SPI inputs
INMISO - SPI output (to controller)
--
Whats are the word lengths used by the SPI link?
16-bit words? 32-bit word?

Have a test jig almost ready. How can I past images to the forum?

intron

Intron,

try an image hosting site like imgur.com

UPDATE: looking at the pad diagram, it looks to me like IOVDD is to send a logical 1 back as output (1.8V), and logical 0 output is GND.

Thanks. A quick draw of a bitfury test jig can be found here:



intron
sr. member
Activity: 266
Merit: 251
Whats are the word lengths used by the SPI link?
16-bit words? 32-bit word?

Let me explain protocol.

It is not realtime - so you just prepare bulk buffer, then you execute transmit-receive operation, store buffer and then parse it.
So you can use 32-bit SPI while data could be aligned differently within frames.

SPI RESET sequence - rise MOSI and toggle SCK - that is treated as reset command and by default turns on chain of chips (i.e. all inputs are put to outputs OUT - chip is chaining)

Then - instructions for chaining accepted on bit-level

0 - is NOP - no instruction and ignored
100 - is 'break' chain - it is first broadcasted through whole chain and then - on final clock cycle chain is broken.
101 - establish asynchronous chain to next chip - all of SPI fill be forwarded to next chip in chain
110 - establish synchronous chain to next chip - the same as asynchronous but with additional registers for data - bits will be delayed by 2 in output! so give nop padding to frame of long chains
111 - DATA instruction
data instruction contains 1 byte that that has length in 32-bit words
and 16-bit address

So within single frame you can access any chip and execute data transmissions by to its internal addresses and get results using emit_data function.
For testing purpose - just break chain after reset and start talking to FIRST chip ALWAYS. SPI RESET is synchronization routine, because chip doesn't have global asynchronous reset and starts in undefined state. It is pretty safe however just to send many zeroes to overflow counters inside and get "in sync" with single chip.

----- Communication code snippet ----
unsigned char spibuf[16384]; /* Spi output buffer */
unsigned spibufsz = 0; /* Spi buffer size in bytes */
unsigned nonemit_value[128];
unsigned nonemit_pos[128];
unsigned nonemit_last = 0;

void emit_buf_reverse(const char *str, unsigned sz)
{
        unsigned i;
        for (i = 0; i < sz; i++) { // Reverse bit order in each byte!
                unsigned char p = str;
                p = ((p & 0xaa)>>1) | ((p & 0x55) << 1);
                p = ((p & 0xcc)>>2) | ((p & 0x33) << 2);
                p = ((p & 0xf0)>>4) | ((p & 0x0f) << 4);
                spibuf[spibufsz+i] = p;
        }
        spibufsz += sz;
        printf("Adding %u to %u bytes (reverse)\n", sz, spibufsz);
}
void emit_buf(const char *str, unsigned sz)
{
        unsigned i;
        memcpy(&spibuf[spibufsz], str, sz); spibufsz += sz;
        printf("Adding %u to %u bytes\n", sz, spibufsz);
}

void emit_break(void) { emit_buf("\x4", 1); }
void emit_fsync(void) { emit_buf("\x6", 1); }
void emit_fasync(void) { emit_buf("\x5", 1); }
void emit_data(uint16_t addr, const char *buf, uint16_t len)
{
        unsigned char otmp[3];
        if (len < 4 || len > 128) return; /* This cannot be programmed in single frame! */
        len /= 4; /* Strip */
        otmp[0] = (len - 1) | 0xE0;
        otmp[1] = addr >> 8; otmp[2] = addr & 0xFF;
        emit_buf(otmp, 3);
        emit_buf_reverse(buf, len*4);
}
-------------------------------

that's it ? Is it clear to everyone ?
legendary
Activity: 1176
Merit: 1001
CryptoTalk.Org - Get Paid for every Post!
IOVDD - feed it with 1.8 V
--
This is for IO with the processor I guess? Can it be 3V3 also?

INCLK - input clock (in case if internal oscillator not works)
--
What clock frequency?

INMOSI, INSCK - SPI inputs
INMISO - SPI output (to controller)
--
Whats are the word lengths used by the SPI link?
16-bit words? 32-bit word?

Have a test jig almost ready. How can I past images to the forum?

intron

Intron,

try an image hosting site like imgur.com

UPDATE: looking at the pad diagram, it looks to me like IOVDD is to send a logical 1 back as output (1.8V), and logical 0 output is GND.
sr. member
Activity: 389
Merit: 250
Observing, bitfury is a good option. Bitfury vs KNC. But Russia is different.
sr. member
Activity: 686
Merit: 250
I am very interested in this.
Own a mobile phone repair shop, guess everything needed is available.
Would like to test them, minimum chip sample.
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