[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 56.

Eric Muyser

full member

Activity: 224

Merit: 100

You can't kill math.

bitfury, about your bet, it was edited by BitBet staff right? You did not write this part?

Quote

BitFury's ASIC will be demonstrated to mine Bitcoin either publicly, in an open to the public event announced at least two weeks in advance, or privately as confirmed by unaffiliated, well respected members of the community (this specifically excludes known shills such as Luke-jr) and will consume less than 1 W per GH/s for powering the chip and the board (excluding any cooling appliances). CHIP ZARABOTAET I BUDET POTREBLYAT < 1 W / GH/s. Initiated by Bitfury, who placed the first Yes bet.

bitfury

sr. member

Activity: 266

Merit: 251

Quote from: MrTeal on June 08, 2013, 12:29:26 AM

Quote from: GalaxyASIC on June 08, 2013, 12:23:13 AM

Quote from: bitfury on June 07, 2013, 11:30:46 PM

Quote from: GalaxyASIC on June 07, 2013, 11:20:51 PM

How many cores are in the chip and how many clock cycles does it take to get a result?
Does each core has GPIO or is there some serial but that aggregates them?
Does your QFN48 7x7mm packaging has exposed thermal pad and is it on top or bottom?

1. 756 double sha256 cores. 61+4 kernel (61 clock cycle computation 4 clock cycle load).

2. There's asynchronous 'match' signal - the only thing that core sends out. And some busses to load data.

3. wirebond. die is laid normally in cavity. i.e. it is not flip-chip and not arranged to give heat into anything else, but PCB.
It is actually not complex to dissipate 3W... Maybe even 5W with metal-core PCB and proper cooling. That's what we'll see.

756 double cores in 7x7mm package?, how many gates approximately in each double core and what are the die dimensions?

You should probably read a little on the design philosophy bitfury used in his previous FPGA design. I believe he fit 82 cores in an LX150.

die dimensions - 3.8x3.8 mm
160x99um approx. kernel size (that's two sha256).
dimensions are as in die (scaled down to 55nm from 65nm).

Gates - I cannot say easily that's full-custom design and can't extract that count easily. NAND2 approximation would be 4, but my cells are actually more complex.
Number of non-cap transistors found from cell kern32: 54558

And... there's still some things can be done better, but more risky - it's kind conservative design as I am doing this first time in my life and want to have as best success chances as I may get.
So it can be done better - but that's I think is what I'll do for smaller tech nodes. Also... 15% of die went to auxiliary circuits such as padframe, ESD, some control, etc.

Sitarow

legendary

Activity: 1792

Merit: 1047

Keep up the great work Bitfury.

MrTeal

legendary

Activity: 1274

Merit: 1004

Quote from: GalaxyASIC on June 08, 2013, 12:23:13 AM

Quote from: bitfury on June 07, 2013, 11:30:46 PM

Quote from: GalaxyASIC on June 07, 2013, 11:20:51 PM

How many cores are in the chip and how many clock cycles does it take to get a result?
Does each core has GPIO or is there some serial but that aggregates them?
Does your QFN48 7x7mm packaging has exposed thermal pad and is it on top or bottom?

1. 756 double sha256 cores. 61+4 kernel (61 clock cycle computation 4 clock cycle load).

2. There's asynchronous 'match' signal - the only thing that core sends out. And some busses to load data.

3. wirebond. die is laid normally in cavity. i.e. it is not flip-chip and not arranged to give heat into anything else, but PCB.
It is actually not complex to dissipate 3W... Maybe even 5W with metal-core PCB and proper cooling. That's what we'll see.

756 double cores in 7x7mm package?, how many gates approximately in each double core and what are the die dimensions?

You should probably read a little on the design philosophy bitfury used in his previous FPGA design. I believe he fit 82 cores in an LX150.

Gomeler

hero member

Activity: 697

Merit: 500

Interested in a few chips AFTER the testing is completed. I'm just a hobbyist, can't actually provide any useful feedback but would enjoy buying a few chips to make some 1-4 chip devices for fun. Congratulations guys, I hope it works!

GalaxyASIC

full member

Activity: 130

Merit: 100

Quote from: bitfury on June 07, 2013, 11:30:46 PM

Quote from: GalaxyASIC on June 07, 2013, 11:20:51 PM

How many cores are in the chip and how many clock cycles does it take to get a result?
Does each core has GPIO or is there some serial but that aggregates them?
Does your QFN48 7x7mm packaging has exposed thermal pad and is it on top or bottom?

1. 756 double sha256 cores. 61+4 kernel (61 clock cycle computation 4 clock cycle load).

2. There's asynchronous 'match' signal - the only thing that core sends out. And some busses to load data.

3. wirebond. die is laid normally in cavity. i.e. it is not flip-chip and not arranged to give heat into anything else, but PCB.
It is actually not complex to dissipate 3W... Maybe even 5W with metal-core PCB and proper cooling. That's what we'll see.

756 double cores in 7x7mm package?, how many gates approximately in each double core and what are the die dimensions?
So there is no metal pad in or on the package to move the heat from silicone? Just plastic all around the die?

wonko

full member

Activity: 155

Merit: 100

I would love to give these a test. I'm an electrical engineer by trade and have an entire EE lab at my disposal to get some of these up and running Grin

Let me know

Eric Muyser

full member

Activity: 224

Merit: 100

You can't kill math.

Quote from: bitfury on June 07, 2013, 10:42:19 PM

Quote from: GalaxyASIC on June 07, 2013, 10:32:14 PM

Congrats on making a chip so fast, even though I am technically your competitor, I am happy for the whole eco system.

Here is why everyone who bet on Bitbet that your chip will run "< 1 W / GH/s" will loose:
....

Thanks, but .... we may still loose technically because there's 15th June to give proof and bitbet.us says it can't extend resolution time unfortunately, it's a bit unfair as mainly packing screw up... At least unfair to those who placed bets... I think that I will compensate to all who bet for 'Yes' in case if chip works as expected, so they would get expected betting returns. As this is pretty my responsibility for delays.

Wow really? That's really nice if you do.

Good luck!

MrTeal

legendary

Activity: 1274

Merit: 1004

I am very interested in this. I'm currently developing a miner using another ASIC chip, but would love to try out another device if for nothing else than due diligence.

I will PM you details.

newmars

full member

Activity: 154

Merit: 100

observing

bitfury

sr. member

Activity: 266

Merit: 251

Quote from: GalaxyASIC on June 07, 2013, 11:20:51 PM

How many cores are in the chip and how many clock cycles does it take to get a result?
Does each core has GPIO or is there some serial but that aggregates them?
Does your QFN48 7x7mm packaging has exposed thermal pad and is it on top or bottom?

1. 756 double sha256 cores. 61+4 kernel (61 clock cycle computation 4 clock cycle load).

2. There's asynchronous 'match' signal - the only thing that core sends out. And some busses to load data.

3. wirebond. die is laid normally in cavity. i.e. it is not flip-chip and not arranged to give heat into anything else, but PCB.
It is actually not complex to dissipate 3W... Maybe even 5W with metal-core PCB and proper cooling. That's what we'll see.

auto2nr1

sr. member

Activity: 350

Merit: 250

This is great news! Looking forward to the test results.

nbtcminer

sr. member

Activity: 249

Merit: 250

Reserved

polrpaul

full member

Activity: 238

Merit: 100

Love the Bitcoin.

reserved

GalaxyASIC

full member

Activity: 130

Merit: 100

How many cores are in the chip and how many clock cycles does it take to get a result?
Does each core has GPIO or is there some serial but that aggregates them?
Does your QFN48 7x7mm packaging has exposed thermal pad and is it on top or bottom?

Edit: I see you answered above some of the questions, please answer the other once.

FCTaiChi

sr. member

Activity: 308

Merit: 250

decentralizedhashing.com

I'm more impressed with BitFury every day, I'll gather their info for the list... I haven't seen anyone give credible evidence of anything wrong with their information.

stripykitteh

legendary

Activity: 1176

Merit: 1001

CryptoTalk.Org - Get Paid for every Post!

reserved

EDIT: PM sent.

bitfury

sr. member

Activity: 266

Merit: 251

Quote from: fasmax on June 07, 2013, 10:58:50 PM

How many leads does the chip have and what package type ?

QFN48 7x7 mm plastic package.

Pad diagram: https://mega.co.nz/#!SctDlaJY!TMVG_E6gOVI-MMky8BS0hTy_h-AqpBeVfgrKF_d0J7g

central pad - ground
35 pads - VDD - on three sides - core voltage - 0.6 .. 0.9 V with high amperage.

I/O (required for testing):

IOVDD - feed it with 1.8 V
IOREF - feed it with 0.9 V for standard signalling (better not take VDD but put resistive divider between GND and IOVDD) and some cap to remove pulsations.
INCLK - input clock (in case if internal oscillator not works)

INMOSI, INSCK - SPI inputs
INMISO - SPI output (to controller)

then 'bonus' pins for further testing are:

OUTCLK, OUTSCK, OUTMOSI, OUTMISO - are for chaining SPI communication to next chip (chaining mode is programmable within chip). OUTMISO should be tied to GND.

and

CMQ, CMPLUS, CMMINUS - are internal regulator. it is beyond the scope right now as it could be rocket science to make it work using realistic noise... these should be tied to GND.

If mounting is dead-bug - don't forget to solder FAT THICK WIRE to center of the chip to dissipate power! Otherwise you'll prepare "fried chips" food

mwally

newbie

Activity: 21

Merit: 0

This is great news. We're a US based group of technologists and engineers. We've been talking to bitfury during the past few months of their ASIC development and are very excited that they are finally on their way.
We're working with a group of engineers and firmware developers who have finished their last hardware project, bladeRF @ nuand.com. These guys have experience with embedded hardware, FPGA and hardware design.
We'd be delighted at the opportunity to test and evaluate these chips and think that yet another player in the ASIC market is good news for bitcoin.

fasmax

sr. member

Activity: 378

Merit: 250

How many leads does the chip have and what package type ?

Topic: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 56. (Read 176727 times)