[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 8.

gingernuts

member

Activity: 89

Merit: 10

Quote from: KNK on November 08, 2013, 02:36:46 AM

Quote from: gingernuts on November 07, 2013, 04:35:51 PM

Loving the use of strip-board - you must be a glutton for punishment! Shocked

It takes 2 weeks to wait a for a board ... just to find out you've messed something Sad

I've made a small board for just the chip with caps - the rest is easy to be put even on a strip-bard and this way i could also swap the chips at will and test the differences between them.
Now I am (almost) sure the prototype will work as expected

Does your small board even have solder-resist? I'm very impressed if you managed to put the QFN's down without it!

gingernuts

member

Activity: 89

Merit: 10

Quote from: vs3 on November 07, 2013, 11:15:05 PM

Quote from: goodney on November 07, 2013, 02:20:49 PM

Quote from: gingernuts on November 07, 2013, 04:39:02 AM

That was my plan with the CPLD - 1.8v I/O within each board, 3.3v between them and the controller board.

Unfortunately I didn't think through the implications of powering the rpi independently of the 3.3v to the board during bring up - I wanted to be able to measure the board's 3.3v draw. Unfortunately if you power the rpi up before the board, you send 3.3v into an unpowered I/O pin on the CPLD and the chip goes into latchup Sad

I would have liked to have c-scape in my design review to say 'you don't want to do it like that!' Wink

That seems like a short coming or bug in the CPLD. A CPLD with 3.3V tolerant I/O shouldn't care what the state of the pins are when it powers up... which CPLD did you use?

which is why I picked to go with the KISS Principle - a few resistors, one transistor and that's all - very very few things to go wrong

Well, I was going for the more-integration => less to go wrong side of the KISS principle, seems your version was more successful this time round!

cscape

sr. member

Activity: 251

Merit: 250

Quote from: KNK on November 08, 2013, 02:36:46 AM

It takes 2 weeks to wait a for a board ... just to find out you've messed something Sad

That's why I ordered my board in June. Cool

KNK

hero member

Activity: 692

Merit: 502

Quote from: gingernuts on November 07, 2013, 04:35:51 PM

Loving the use of strip-board - you must be a glutton for punishment! Shocked

It takes 2 weeks to wait a for a board ... just to find out you've messed something Sad

I've made a small board for just the chip with caps - the rest is easy to be put even on a strip-bard and this way i could also swap the chips at will and test the differences between them.
Now I am (almost) sure the prototype will work as expected

vs3

hero member

Activity: 622

Merit: 500

Quote from: goodney on November 07, 2013, 02:20:49 PM

Quote from: gingernuts on November 07, 2013, 04:39:02 AM

That was my plan with the CPLD - 1.8v I/O within each board, 3.3v between them and the controller board.

Unfortunately I didn't think through the implications of powering the rpi independently of the 3.3v to the board during bring up - I wanted to be able to measure the board's 3.3v draw. Unfortunately if you power the rpi up before the board, you send 3.3v into an unpowered I/O pin on the CPLD and the chip goes into latchup Sad

I would have liked to have c-scape in my design review to say 'you don't want to do it like that!' Wink

That seems like a short coming or bug in the CPLD. A CPLD with 3.3V tolerant I/O shouldn't care what the state of the pins are when it powers up... which CPLD did you use?

which is why I picked to go with the KISS Principle - a few resistors, one transistor and that's all - very very few things to go wrong

gingernuts

member

Activity: 89

Merit: 10

Quote from: KNK on November 07, 2013, 03:09:15 PM

As promised:

It is not possible to get a good focus with a mobile, but this

is the level shifter, not a death bug on my desk

Loving the use of strip-board - you must be a glutton for punishment! Shocked

gingernuts

member

Activity: 89

Merit: 10

Quote from: goodney on November 07, 2013, 02:20:49 PM

Quote from: gingernuts on November 07, 2013, 04:39:02 AM

That was my plan with the CPLD - 1.8v I/O within each board, 3.3v between them and the controller board.

Unfortunately I didn't think through the implications of powering the rpi independently of the 3.3v to the board during bring up - I wanted to be able to measure the board's 3.3v draw. Unfortunately if you power the rpi up before the board, you send 3.3v into an unpowered I/O pin on the CPLD and the chip goes into latchup Sad

I would have liked to have c-scape in my design review to say 'you don't want to do it like that!' Wink

That seems like a short coming or bug in the CPLD. A CPLD with 3.3V tolerant I/O shouldn't care what the state of the pins are when it powers up... which CPLD did you use?

Yeah, I'm a bit surprised they're so easy to damage...

I'm using a Xilinx xc2c64 - once I've swapped this dead one out, I'll make sure I take the 3.3v feed from the rpi.

KNK

hero member

Activity: 692

Merit: 502

As promised:

It is not possible to get a good focus with a mobile, but this

is the level shifter, not a death bug on my desk

goodney

member

Activity: 102

Merit: 10

Quote from: gingernuts on November 07, 2013, 04:39:02 AM

That was my plan with the CPLD - 1.8v I/O within each board, 3.3v between them and the controller board.

Unfortunately I didn't think through the implications of powering the rpi independently of the 3.3v to the board during bring up - I wanted to be able to measure the board's 3.3v draw. Unfortunately if you power the rpi up before the board, you send 3.3v into an unpowered I/O pin on the CPLD and the chip goes into latchup Sad

I would have liked to have c-scape in my design review to say 'you don't want to do it like that!' Wink

That seems like a short coming or bug in the CPLD. A CPLD with 3.3V tolerant I/O shouldn't care what the state of the pins are when it powers up... which CPLD did you use?

KNK

hero member

Activity: 692

Merit: 502

Quote from: cscape on November 07, 2013, 12:27:50 AM

Quote from: goodney on November 06, 2013, 08:25:04 PM

Fun discussion, you guys would be no fun in a design review ;-p

If it was an early design review, it would be fun

I'll post a picture of my test design latter when i get home. It is fun ... particularly the level-shifter

gingernuts

member

Activity: 89

Merit: 10

Quote from: goodney on November 06, 2013, 08:25:04 PM

cscape is of course 100% right, but hey, I work on these things late at night after the kids are asleep... so level shifters: if one is good, then two must be better. Also, you could make an argument that when driving board-to-board 3.3V has a better noise margin than 1.8V.

That was my plan with the CPLD - 1.8v I/O within each board, 3.3v between them and the controller board.

Unfortunately I didn't think through the implications of powering the rpi independently of the 3.3v to the board during bring up - I wanted to be able to measure the board's 3.3v draw. Unfortunately if you power the rpi up before the board, you send 3.3v into an unpowered I/O pin on the CPLD and the chip goes into latchup Sad

I would have liked to have c-scape in my design review to say 'you don't want to do it like that!' Wink

cscape

sr. member

Activity: 251

Merit: 250

Quote from: goodney on November 06, 2013, 08:25:04 PM

Fun discussion, you guys would be no fun in a design review ;-p

If it was an early design review, it would be fun

goodney

member

Activity: 102

Merit: 10

Quote from: KNK on November 06, 2013, 03:27:41 PM

74AVC4T245 is what i am testing the chips with and the reason for adding ActiveLowOE, but you did it the wrong way with two chips i think, because you won't be able to control two banks separately that way ... except if you use the two groups of each chips for two separate banks, but then why not just make them as In/Out on the same chip and the other one for the next bank?

I'm not trying to do banks, my board is a single chip development board, main purpose: learn to use Altium. 2nd purpose: a board to experiment with (hardware and software) so I can make larger more sophisticated boards in the future.

Quote from: KNK on November 06, 2013, 03:27:41 PM

Quote from: cscape on November 06, 2013, 02:16:24 PM

For chaining you just connect 2nd chip to 1st chip without level shifters. The whole chain runs at 1.8V, and you only need to convert to 3.3V between first chip and host.

As cscape said - chaining the chips is by connecting the first chip outputs to the second chip inputs without any level shifters. You need different LS for the different banks only and then you enable each bank by it's own OE

With some crazy wiring (board design) you may even go for 3 banks with only 2 LS if you want to be stingy

cscape is of course 100% right, but hey, I work on these things late at night after the kids are asleep... so level shifters: if one is good, then two must be better. Also, you could make an argument that when driving board-to-board 3.3V has a better noise margin than 1.8V.

Anyways, all moot points as this version of the board will never get fabbed again, and it has met several goals, one of which is proving out the power supply design.

Fun discussion, you guys would be no fun in a design review ;-p

-a[g

KNK

hero member

Activity: 692

Merit: 502

Quote from: goodney on November 06, 2013, 02:14:45 PM

I have two level shifters so that I could support chaining with my board. One chip does 3.3->1.8 (inputs) and one does 1.8->3.3 (outputs). They are 74AVC4T245's

74AVC4T245 is what i am testing the chips with and the reason for adding ActiveLowOE, but you did it the wrong way with two chips i think, because you won't be able to control two banks separately that way ... except if you use the two groups of each chips for two separate banks, but then why not just make them as In/Out on the same chip and the other one for the next bank?

Quote from: cscape on November 06, 2013, 02:16:24 PM

For chaining you just connect 2nd chip to 1st chip without level shifters. The whole chain runs at 1.8V, and you only need to convert to 3.3V between first chip and host.

As cscape said - chaining the chips is by connecting the first chip outputs to the second chip inputs without any level shifters. You need different LS for the different banks only and then you enable each bank by it's own OE

With some crazy wiring (board design) you may even go for 3 banks with only 2 LS if you want to be stingy

cscape

sr. member

Activity: 251

Merit: 250

For chaining you just connect 2nd chip to 1st chip without level shifters. The whole chain runs at 1.8V, and you only need to convert to 3.3V between first chip and host.

goodney

member

Activity: 102

Merit: 10

Quote from: KNK on November 06, 2013, 01:59:34 PM

Why do you have two chips for level shifting and what are they (can't see from the picture)?
For SCK and MOSI a resistor divider should be enough for single bank/chip. Also instead of the blue wires couldn't you just swap the wires going to the RPi at the top left of the board?

I have two level shifters so that I could support chaining with my board. One chip does 3.3->1.8 (inputs) and one does 1.8->3.3 (outputs). They are 74AVC4T245's

I couldn't just swap the RPi wires because I had fixed the direction of the level shifters on the PCB and I had MISO on the "input" converter. So I ended up having to swap MISO from the BF to the "output" level converter, and swap the RPi wire. One of the "fixes" on the board is because I cut the wrong trace. Don't start cutting traces right before lunch.

BTW, thanks for the cgminer fork. I get better results than chainminer (w/ proxy) and BFGMiner didn't work at all.

-a[g

KNK

hero member

Activity: 692

Merit: 502

Quote from: goodney on November 06, 2013, 01:28:11 PM

The FuryBug hashes!

Thought you guys might like an update on my little dev board. As you can see from the pictures I managed to mess up the schematic a little bit, hence the teeny-tiny blue wires. The Xacto knife is your friend.

I'm using KNK's cgminer fork which detects my single chip as a Bank 0, chip 0. Long term average 2GH/s.

FYI, gingernuts, the CPLD as a level shifter is genius. That would have saved me a ton of time.

Why do you have two chips for level shifting and what are they (can't see from the picture)?
For SCK and MOSI a resistor divider should be enough for single bank/chip. Also instead of the blue wires couldn't you just swap the wires going to the RPi at the top left of the board?

P.S. I have just uploaded another change to my fork which adds support to level shifters with active low for the OE too (like TI SN74AVC4Txxx).
The next step is support for line decodes for the OE (2:4, 3:8 or 4:16) - this way you can have (for example) 8 separate banks with just 3 GPIO's from RPi by simply using 74HC138 or 74HC238 depending on the level shifter in use

goodney

member

Activity: 102

Merit: 10

The FuryBug hashes!

Thought you guys might like an update on my little dev board. As you can see from the pictures I managed to mess up the schematic a little bit, hence the teeny-tiny blue wires. The Xacto knife is your friend.

I'm using KNK's cgminer fork which detects my single chip as a Bank 0, chip 0. Long term average 2GH/s.

FYI, gingernuts, the CPLD as a level shifter is genius. That would have saved me a ton of time.

gingernuts

member

Activity: 89

Merit: 10

I blew up my 1st board by stupidly hooking up my rpi back to front and sending 5v somewhere it should never have gone!

Assembled and reflowed another prototype tonight, and the reset sequence seems to be doing something - not getting any sensible SPI out but current draw shoots up and I seem to have reset sequence coming out the end of the chain. MISO from 1st chip isn't doing anything though Sad

More debugging required tomorrow.

vs3 - thanks for open sourcing your project, I haven't looked at your thread yet, but I'm sure it will be a good read!

vs3

hero member

Activity: 622

Merit: 500

Gingernuts - that's why I wanted to stick with the "KISS Principle"

No RPi, no CPLDs, no extra processors, etc, etc, etc.

Just plain old - "Keep It Simple" - Stuff!

By the way - several people had asked me about the NanoFury design, so I figured it would be most appropriate if I start my own topic:

NanoFury Project - Open Source Design

It also just hurts watching so many people suffer with the same issues that I had - hopefully that project will be of some help.

Topic: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE! - page 8. (Read 176742 times)