[ANN]ASICMiner Publicly Looking for Potential Customers/Partners for New Chips

dhenson

legendary

Activity: 994

Merit: 1000

Quote from: tinyfox266 on July 30, 2014, 02:56:13 AM

Quote from: dhenson on July 29, 2014, 11:26:13 PM

Quote from: Phasebird on July 29, 2014, 12:26:38 PM

This ID is in charge of the sales of AM-GEN3-MINERS.

Our official-miners are coming soon.

All resellers interested in it please msg us for more info.

Phasebird,

Are you an official employee of bitfountain/Asicminer?

He is.

https://bitcointalksearch.org/topic/m.8079873

Perhaps I could have worded my post more clearly. Shareholders have been asking for Friedcat to appoint a community liaison for a long time. It would appear that we may finally have been granted one, but yet it is not widely known and that liaison has not introduced himself to the main thread. It would appear that not many know he is even here.

This is not the thread for this discussion so I will end by simply suggesting that Phasebird make his position known and give us some idea of the scope of his responsibilities. It is possible that he is simply as friedcat said, responsible for the re-seller communication and questions regarding the meetup.

tinyfox266

member

Activity: 67

Merit: 10

Quote from: dhenson on July 29, 2014, 11:26:13 PM

Quote from: Phasebird on July 29, 2014, 12:26:38 PM

This ID is in charge of the sales of AM-GEN3-MINERS.

Our official-miners are coming soon.

All resellers interested in it please msg us for more info.

Phasebird,

Are you an official employee of bitfountain/Asicminer?

He is.

https://bitcointalksearch.org/topic/m.8079873

dhenson

legendary

Activity: 994

Merit: 1000

Quote from: Phasebird on July 29, 2014, 12:26:38 PM

This ID is in charge of the sales of AM-GEN3-MINERS.

Our official-miners are coming soon.

All resellers interested in it please msg us for more info.

Phasebird,

Are you an official employee of bitfountain/Asicminer? Are you the community relations person we have been waiting patiently (well, mostly patiently) for?

If so, please introduce yourself on the main thread... We have tons of questions.

jjj0923

sr. member

Activity: 266

Merit: 250

congratulations!

Quote from: marto74 on July 05, 2014, 12:49:07 PM

Test Board
hashing

Phasebird

newbie

Activity: 47

Merit: 0

This ID is in charge of the sales of AM-GEN3-MINERS.

Our official-miners are coming soon.

All resellers interested in it please msg us for more info.

marto74

hero member

Activity: 728

Merit: 500

Test Board
hashing

marto74

hero member

Activity: 728

Merit: 500

Yes "V style" because it is a test board and we left room on the stencil for bigger 1210 caps .
At the moment there are 0603 470nF ones, that can be exchanged with 1206 1uF or 1210 upt to 220uf if needed.
Usualy on the boards we put a lot of pads that way we can exchange components if there is trouble during the test or in production if the there is no stock.
Same way is with part of ICs we can put 2 different footprints of transistor drivers or 2 different footprints of 3.3 and 5 V regs.
The when the production starts we make anew stencil only for the components we are about to place

antirack

hero member

Activity: 489

Merit: 500

Immersionist

Quote from: marto74 on July 03, 2014, 03:22:20 AM

Here is hex16E ( AM Be200) 16 chip board populated.
Let the sleeples nights with tests begin Cheesy

That looks like quality work marto74!

I hope the different BE200 orientation per row is intentional.

(did you notice the placement of many caps is V style?)

bbxx

hero member

Activity: 728

Merit: 500

cryptoshark

is there a chance for beautyfull miner from technobit finally?

marto74

hero member

Activity: 728

Merit: 500

Here is hex16E ( AM Be200) 16 chip board populated.
Let the sleeples nights with tests begin Cheesy

marto74

hero member

Activity: 728

Merit: 500

WE are finishing our design of a 16 chip mining board with ASIC miner BE200 chips

specs
Our own design HEX 16E miner main specs:
- 16 BE200 chip board in 2 rows
- 16 bit Microchip controller with usb control
- Voltage to be adjustable by command in the PIC
- Multi channel power supply
- power connector PCI-e
- capable to run Overclocked

*greetings BICK Tongue

marto74

hero member

Activity: 728

Merit: 500

I got tracking so sample chips are on the way to me Cheesy

Some info about chip sales chanel in the range of 100 , 500, 1k, and so would be useful

CanaryInTheMine

donator

Activity: 2352

Merit: 1060

between a rock and a block!

Quote from: hdbuck on June 07, 2014, 12:09:23 PM

Quote from: CanaryInTheMine on June 07, 2014, 12:00:11 PM

Quote from: thatguy42 on June 06, 2014, 10:35:29 PM

Will these chips ever be available to the public; in reasonable quantities ?
I'm sure www.digikey.com/ or www.jameco.com and others, could sell a fair number.
Any resellers planned for this summer ?

it is planned

canary, if thats not too indiscreet, from whom did you already ordered AMgen3 based products? Rockminer? will you also be reselling AM chips Huh

rockminer. chip sales channels are being developed. ofcourse, a large order can be placed with ASICMiner directly at any time.

hdbuck

legendary

Activity: 1260

Merit: 1002

Quote from: CanaryInTheMine on June 07, 2014, 12:00:11 PM

Quote from: thatguy42 on June 06, 2014, 10:35:29 PM

Will these chips ever be available to the public; in reasonable quantities ?
I'm sure www.digikey.com/ or www.jameco.com and others, could sell a fair number.
Any resellers planned for this summer ?

it is planned

canary, if thats not too indiscreet, from whom did you already ordered AMgen3 based products? Rockminer? will you also be reselling AM chips Huh

CanaryInTheMine

donator

Activity: 2352

Merit: 1060

between a rock and a block!

Quote from: thatguy42 on June 06, 2014, 10:35:29 PM

Will these chips ever be available to the public; in reasonable quantities ?
I'm sure www.digikey.com/ or www.jameco.com and others, could sell a fair number.
Any resellers planned for this summer ?

it is planned

thatguy42

newbie

Activity: 37

Merit: 0

Will these chips ever be available to the public; in reasonable quantities ?
I'm sure www.digikey.com/ or www.jameco.com and others, could sell a fair number.
Any resellers planned for this summer ?

friedcat

donator

Activity: 848

Merit: 1005

Quote from: Luke-Jr on May 28, 2014, 06:19:39 AM

Quote from: friedcat on May 28, 2014, 05:25:59 AM

Quote from: Luke-Jr on May 23, 2014, 05:11:02 PM

Quote from: friedcat on April 20, 2014, 11:16:22 PM

datasheet - https://docs.google.com/document/d/1_dmXzyMqtr7tVZukk2DAJih2sRq5jDy5DQPkwCce570/edit?usp=sharing

Some questions...

What is the behaviour if task address is changed while the chip is busy hashing?

What about when address 44 is changed?

How is nonce_mask to be interpreted?

Is there any safeguard against a race clearing r_ready after reading nonce(s)?
For example, the order of events:

Host reads nonce from chip
Chip finds new nonce
Host clears r_ready

1) 2) When the chip is busy hashing the values in task addresses (including 44) cannot be changed.

3) Each 1 in the nonce_mask indicates a nonce for the current job. If the number of nonces exceeds 4, the first ones will be dropped.

4) There aren't safeguards.

For 1) and 2) we suggest a higher SPI clock for better efficiency. Using the difficulty setting larger than 1 could alleviate most hashrate losses caused by 3) and 4).

Hmm, is there any way to tell the chip to abort processing a work then?
Or we just need to wait it out?

The soft reset can be triggered no matter if the chip is working or not. After that you need to reconfigure the PLL though, which will take about 0.2ms.

Luke-Jr

legendary

Activity: 2576

Merit: 1186

Quote from: friedcat on May 28, 2014, 05:25:59 AM

Quote from: Luke-Jr on May 23, 2014, 05:11:02 PM

Quote from: friedcat on April 20, 2014, 11:16:22 PM

datasheet - https://docs.google.com/document/d/1_dmXzyMqtr7tVZukk2DAJih2sRq5jDy5DQPkwCce570/edit?usp=sharing

Some questions...

What is the behaviour if task address is changed while the chip is busy hashing?

What about when address 44 is changed?

How is nonce_mask to be interpreted?

Is there any safeguard against a race clearing r_ready after reading nonce(s)?
For example, the order of events:

Host reads nonce from chip
Chip finds new nonce
Host clears r_ready

1) 2) When the chip is busy hashing the values in task addresses (including 44) cannot be changed.

3) Each 1 in the nonce_mask indicates a nonce for the current job. If the number of nonces exceeds 4, the first ones will be dropped.

4) There aren't safeguards.

For 1) and 2) we suggest a higher SPI clock for better efficiency. Using the difficulty setting larger than 1 could alleviate most hashrate losses caused by 3) and 4).

Hmm, is there any way to tell the chip to abort processing a work then?
Or we just need to wait it out?

marto74

hero member

Activity: 728

Merit: 500

Any chance I get an answer to my mails and PM's about sample chips , datasheet , pricing etc.

friedcat

donator

Activity: 848

Merit: 1005

Quote from: Luke-Jr on May 23, 2014, 05:11:02 PM

Quote from: friedcat on April 20, 2014, 11:16:22 PM

datasheet - https://docs.google.com/document/d/1_dmXzyMqtr7tVZukk2DAJih2sRq5jDy5DQPkwCce570/edit?usp=sharing

Some questions...

What is the behaviour if task address is changed while the chip is busy hashing?

What about when address 44 is changed?

How is nonce_mask to be interpreted?

Is there any safeguard against a race clearing r_ready after reading nonce(s)?
For example, the order of events:

Host reads nonce from chip
Chip finds new nonce
Host clears r_ready

1) 2) When the chip is busy hashing the values in task addresses (including 44) cannot be changed.

3) Each 1 in the nonce_mask indicates a nonce for the current job. If the number of nonces exceeds 4, the first ones will be dropped.

4) There aren't safeguards.

For 1) and 2) we suggest a higher SPI clock for better efficiency. Using the difficulty setting larger than 1 could alleviate most hashrate losses caused by 3) and 4).

Topic: [ANN]ASICMiner Publicly Looking for Potential Customers/Partners for New Chips (Read 54971 times)