Topic: [Announcement] Avalon ASIC Development Status [Batch #1] - page 25. (Read 155346 times)

Don't forget to overclock.

So I take that picture of the chip layout, print it out on my inkjet printer, glue it to a heatsink, then plug it in to the wall, right? Then I've got gigahashes?

excellent information and updating going on here..  ALL the other ASIC sellers should be taking notes and following along the same line with the detail and information being passed.  Sadly, at this point they are not even in the same ballpark..

Thank you for the Honest as well as Informative post. 

We don't plan to release this information, any information regarding our unit's internal you will have to find from pictures our customers who feels like uploading. This is our trade secret as we feel we designed a truly unique and innovative unit.

Updating as promised,

Let's be frank. We ran into a potential delay of 4-7 days.

What does this mean?

We when taped out the chips to TSMC we had a "projected out date" of Jan 3, 2013 which is on schedule with our late dec. / early jan. demonstration dates. Now however after this week's website update our "projected out date" has changed to Jan 7th, 2013 and "committed date" has been revealed to be Jan 10th, 2013. TSMC did not give us a reason for this, but as a small customer you are really at the mercy of bigger customers running higher priority lots. e.g. "super hot lot"  The "committed date" is the promised date of delivery, it is very unusual for TSMC to break their "committed date", so we expect our chips to ship on or before Jan 10th, 2013.

Another potential problem is Customs clearing, the packaging company Fujitsu is located in Shanghai's Export Processing Zone (EPZ), while the packaging itself will not see delays, it may take an additional 2-3 days to clear Customs. To make up for this, if it occurs, we will be flying down to Shanghai to the demonstration in the EPZ instead of waiting for the shipping to the factory for assembly.

With all this happening, it has burned through the 1 week additional leeway time we originally left out. I must say it will be difficulty for us to ship on Jan 14th, we however expect to ship around Jan 18 ~ 20.

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Since some people were wondering how many chips are on a wafer earlier in the thread after we posted the MT forms I'll tell you, each wafer contains 4055 chips.

and this is the chip layout.

Newsletter time?

sorry, we simply disbelieve it. 


thank you.

bASIC has said they have had demo chips (initial prototype burned out, but they have more chips than were in the prototype), so they have done MPW.

ngzhang, so after you've validated a few initial chips and demo, it's straight to production? hope you guys pull off an ahead of schedule shipping time!

yes

no one use MPW this time. include us, BFL ,bASIC, asicminer, etc.

just like a Chinese network catchword: we are all fighting without pants. (我们都已经脱了裤子干了)

I understood that the demo would be based on a chips coming from a MPW.  Then, if this is successful, a new maskset would be made and full wafers produced using the design, which would go into the products we would receive.

I find it hard to believe that a new tapeout and wafer production can happen in between then and Jan 14, much less board production and everything else that will be needed to ship out the door on Jan 14th.

How has Avalon been able to shortcut this process?  Are they also taking the 'cajones de acero' approach, and like BFL, producing full wafers from the start?

not sure exactly how much time is needed to qc and package, but it looks like by around christmas time asicminer should have chips?


avalon should have theirs around the same time too, right? or even before then if the demo is to occur late Dec.

Yifu, can you comment on your demo timelines? and what will occur between demo and shipping?

Everyone was trying to win the hash race instead of trying to win the time race.  I keep saying it, but no one listens.  The winner of the time race, unless 2 or more manufacturers ship at about the same time, win ALL the marbles.  If BFL could have delivered a mere 15GH at $700, but back in October, they'd be so flooded with pre-orders right now the other folks wouldn't have a chance to catch up.  And while they try, BFL would be jumping ahead by doing nothing more than stacking ASIC's on ASIC's for diminishing costs, leaving Tom and Avalon in their wake.

Any chance Avalon's subsequent batches will move to smaller node and reduce power use? I think they could do well if they are first to market and follow up with lower power consumption.

Thats exactly what I think happened.

They kept trying to compete. Kept raising the bar, kept improving the design. Hell, they are still doing it right now.

I would rather have had my pre-orders running at 30GH/s shipping in October than this.  I only hope that BFL hasn't held back on releasing something that could have run at a lower clock, in order to match the promised specs. Something working is better than something perfect, when time is of the essence.

In addition to everything kaerf's mentioned I think it's worth bringing up that Avalon are superior strategists.  Anyone remember when BFL improved their numbers days after the competition bumped theirs?  BFL fell hook, line and sinker for the release date and stats games from their competition.  Avalon appears to have taken The Art of War to heart.

Update is expected to release on Thursday, or two days from now. We are currently waiting for this round of updates from TSMC for this week which comes tomorrow.