I am not at all familiar with the what is the specific individual nature of the calculation being done in here, so my opinion may be garbage, just replying based on general digital design principles.
It is somewhat common misconception that if clock speed is being increased to cause timing violations in digital logic sense of the word, the result is somewhat predictable to be either the earlier or later value. In general this is not true, the result of the 32 bit word is not any of the right, ealier or later, but it is total garbage. This even what happens in practice. You are not going to get any predictability what the result is going to be.
The reason is that not all bits of a word are finished at the same time in the calculation logic before the latch, some of the bits are going much later to settle to their correct values when you have some bits that arrived much earlier to their new values. Which bits arrive late and which arrive early can also change quite dramatically. The logic can be much faster going from '0' to '1' than going the other way etc.. So in practice the 32 bit word contains some bits that correspond to the correct result and some bits that are from the earlier result. Or it can be even more complex than that. The output bits can fluctuate wildly at the end of the logic doing the calculations and be in transition when the latching occurs. It is possible that some bit that has value '0' in both the correct and earlier result, but is going to have value '1' as some intermediate calculation value before it settles to its new value '0' from the earlier value '0'. It is even possible in theory that the output of the latch after the timing violation is neither '0' or '1'. The latch might become metastable and this metastability could propagate further to the ASIC so big portions of the ASIC could become metastable ( in theory ).
I am not sure you applied these characteristics of what happens in generic timing violations when talking about this specific instance and case.