The controller looks like a plain old SPI + I2C adapter and GPIO button card than anything else to me. The SPI port is used to communicate to all the chips in a chained SPI bus, and the I2C bus is used to communicate to the temp chips.
From what it would seem there is more going on than just that, the bitmain_spi.ko kernel module appears to be built from the following source files. It looks like there is a FPGA of sorts as well that it interfaces with which would explain the fpga source files being a part of the bitmain_spi.ko kernel module.bitmain-asic-drv.c
bitmain-asic.h
fpga.c
fpga.h
sha2.c
sha2.h
spi.c
spi.h
Makefile
Yes, there's an FPGA (An Altera Cyclone 4 specifically, i took some photos and uploaded them here, but they got blatantly ignored). However, Altera Cyclones get programmed with VHDL or Verilog source, not ".c" files, so what you see there is just some verification code from the CGMiner side of things. If/when Bitmain releases their S5 cgminer sources, we can get some more hints about how the communication is done, and would probably get more info about its functionality.
As it stands, i'm pretty much convinced that the FPGA contoller board does at least these things:
- Enumerate the SPI chain (i've connected 4 hashing boards to one controller successfully).
- Communicate via Chained SPI with all the BM1384 chips, at most 120 in total.
- Provide A0-A1-A2 for each hashing board. This corresponds to each BM1384 address pins configuration and would also work for the temp sensor.
- Use I2C to read temps from the onboard sensor.
- Interrupt the beagle bone as nonces come from the SPI chain, as there's no interrupt channel set for this kind of bus, and it would probably needs to busy poll the BM1384s.
